AD5255 datasheet(16/20 Pages) AD

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AD5255

Rev. 0 | Page 16 of 20

USING ADDITIONAL INTERNAL

NONVOLATILE EEPROM

The AD5255 contains additional internal user EEPROM for

saving constants and other data. The user EEPROM I2C data

word follows the same format as the general-purpose EEPROM

memory shown in Figure 19 and Figure 20. User EEPROM

memory addresses are shown in Table 6.

To support the use of multiple EEPROM modules on a single

I2C bus, the AD5255 features two external addressing pins, Pins

21 and 22 (A1_EE and A0_EE) to manually set the address of

the EEPROM included with the AD5255. This feature ensures

that the correct EEPROM memory is accessed when using

multiple memory modules on a single I2C bus.

DIGITAL INPUT/OUTPUT CONFIGURATION

All digital inputs are ESD protected. Digital inputs are high

impedance and can be driven directly from most digital sources.

The RESET digital input pin does not have an internal pull-up

resistor. Therefore, the user should place a pull-up resistor from

RESET to VDD if the function is not used. The WP pin has an

internal pull-down resistor. If not driven by an external source,

the AD5255 defaults to a write-protected state. ESD protection

of the digital inputs is shown in Figure 27.

INPUTS

VDD

GND

Figure 27. Equivalent WP ESD Protection

MULTIPLE DEVICES ON ONE BUS

Figure 28 shows four AD5255 devices on the same serial bus.

Each has a different slave address since the state of their AD0

and AD1 pins are different. This allows independent reading

and writing to each RDAC within each device.

+5V

MASTER

SDA

AD1

AD0

SCL

SDA

AD1

AD0

SCL

SDA

AD1

AD0

SCL

SDA

AD1

AD0

SCL

VDD

Figure 28. Multiple AD5255 Devices on a Single Bus

LEVEL SHIFT FOR BIDIRECTIONAL

COMMUNICATION

While most legacy systems operate at one voltage, adding a new

component might require a different voltage. When two systems

transmit the same signal at two different voltages, use a level

shifter to allow the systems to communicate.

For example, a 3.3 V microcontroller (MCU) can be used along

with a 5 V digital potentiometer. A level shifter is required to

enable bidirectional communication.

Figure 29 shows one of many possible techniques to properly

level-shift signals between two devices. M1 and M2 are

N-channel FETs (2N7002). If VDD falls below 2.5 V, use low

threshold N-channel FETs (FDV301N) for M1 and M2.

VDD1 = 3.3V

VDD2 = 5V

SDA1

SCL1

SDA2

SCL2

3.3V

MCU

AD5255

Figure 29. Level Shifting for Different Voltage Devices on an I2C Bus

TERMINAL VOLTAGE OPERATION RANGE

The AD5255 positive VDD and negative VSS power supply inputs

define the boundary conditions for proper 2-terminal

programmable resistance operation. Supply signals on terminals

W and B that exceed VDD or VSS are clamped by the internal

forward-biased diodes of the AD5255.

VDD

VSS

Figure 30. Maximum Terminal Voltages Set by VDD and VSS

The ground pin of the AD5255 is used as a digital ground

reference, and needs to be tied to the common ground of the

PCB. Reference the digital input control signals to the AD5255

ground pin, and satisfy the logic levels defined in the

Specifications tables.

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