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CY28548 Datasheet(PDF) 2 Page - Silicon Laboratories

Part # CY28548
Description  Clock Generator for Intel짰Crestline Chipset
PDF  31 Pages
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Manufacturer  SILABS [Silicon Laboratories]
Direct Link  http://www.silabs.com
Logo SILABS - Silicon Laboratories

CY28548 Datasheet(HTML) 2 Page - Silicon Laboratories

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CY28548
........................Document #: 001-08400 Rev ** Page 2 of 30
Pin Configuration
64-Pin TSSOP
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
SDATA
SCLK
REF0/FSC/TEST_SEL
VDD_REF
XIN
XOUT
VSS_REF
CKPWRGD/PWRDWN#
FSB/TEST_MODE
CPUT0
CPUC0
VSS_CPU
CPUT1
CPUC1
VDD_CPU_IO
NC
SRCT8/CPU2_ITPT
SRCC8/CPU2_ITPC
VDD_SRC_IO
SRCT7/CR#_F
SRCC7/CR#_E
VSS_SRC
SRCT6
SRCC6
VDD_SRC
PCI_STOP#
CPU_STOP#
VDD_CPU
40
39
38
37
36
35
34
33
VDD_SRC_IO
SRCC10
SRCT10
SRCT11/CR#_H
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
VDD_PCI
PCI0/CR#_A
PCI1/CR#_B
PCI2/TME
PCI3
PCI4/GCLK_SEL
PCIF0/ITP_EN
VDD_48
VSS_PCI
VSS_48
VDD_IO
SRCT0/DOT96T
SRCC0/DOT96C
VSS_IO
VDD_PLL3
SRCT1/LCDT_100/27M_NSS
SRCC1/LCDC_100/27M_SS
VSS_PLL3
VDD_PLL3_IO
SRCT2/SATAT
SRCC2/SATAC
VSS_SRC
SRCT3/CR#_C
SRCC3/CR#_D
VDD_SRC
SRCT4
SRCC4
USB_48/FSA
25
26
27
28
29
30
31
32
VSS_SRC_IO
SRCT9
SRCC9
SRCC11/CR#_G
64-Pin QFN
QFN Pin Definitions
Pin No.
Name
Type
Description
1
VSS_REF
GND
Ground for outputs.
2
Xout
O, SE 14.318 MHz Crystal output.
3Xin
I
14.318 MHz Crystal input.
4
VDD_REF
PWR
3.3V Power supply for outputs and maintains SMBUS registers during power
down.
5
REF0 / FSC / TEST_SEL
I/O
Fixed 14.318 clock output/3.3V-tolerant input for CPU frequency selection/
Selects test mode if pulled to VIHFS_C when CK_PWRGD is asserted HIGH.
Refer to DC Electrical Specifications table for VILFS_C, VIMFS_C, VIHFS_C specifica-
tions.
6SDATA
I/O
SMBus compatible SDATA.
7SCLK
I
SMBus compatible SCLOCK.



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