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CY28548 Datasheet(PDF) 22 Page - Silicon Laboratories

Part # CY28548
Description  Clock Generator for Intel짰Crestline Chipset
PDF  31 Pages
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Manufacturer  SILABS [Silicon Laboratories]
Direct Link  http://www.silabs.com
Logo SILABS - Silicon Laboratories

CY28548 Datasheet(HTML) 22 Page - Silicon Laboratories

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CY28548
......................Document #: 001-08400 Rev ** Page 22 of 30
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1101
N/A
N/A
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Table 8. PLL3/SE Configuration Table (continued)
GCLK_SEL
B1b4
B1b3
B1b2
B1b1
Pin 27 (17) MHz Pin 25 (18) MHz Spread (%)
Comment
Figure 12. Clock Generator Power up/Run State Diagram
FSC
FSB
FSA
Off
Latches Open
M1
T_delay3
Off
Off
3.3V
T_delay t
C l ock O ff to M 1
CPU_STOP#
PCI_STOP#
Vcc
CKPWRGD/PWRDWN
CK505 SMBUS
CK505 State
BSEL[0..2]
CK505 Core Logic
PLL1
CPU1
PLL2 & PLL3
All Other Clocks
REF Oscillator
T_delay2
Locked
2.0V
Figure 13. BSEL Serial Latching



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