CY28548 datasheet(3/31 Pages) SILABS

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CY28548

........................Document #: 001-08400 Rev ** Page 3 of 30

PCI0 / CR#_A

I/O, SE 33 MHz Clock/3.3V Clock Request # Input

Mappable via I2C to control either SRC 0 or SRC 2. Default PCI0.

To configure this pin to serve as a Clock Request pin for either SRC pair 2 or pair

0 using the CR#_A_EN bit located in byte 5 bit 7, first disable PCI output (Hi-z) in

byte 2, bit 1.

0 = PCI0 enabled (default)

1= CR#_A enabled.

Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair

Byte 5, bit 6:

0 = CR#_A controls SRC0 pair (default)

1= CR#_A controls SRC2 pair

VDD_PCI

PWR

3.3V power supply for PCI PLL

PCI1 / CR#_B

I/O, SE 33 MHz Clock/3.3V Clock Request # Input

Mappable via I2C to control either SRC 1 or SRC 4. Default PCI1.

To configure this pin to serve as a Clock Request pin for either SRC pair 1 or pair

4 using the CR#_B_EN bit located in byte 5, bit 5, first disable PCI output (Hi-z) in

byte 2, bit 1.

0 = PCI1 enabled (default)

1= CR#_B enabled.

Byte 5, bit 4 controls whether CR#_B controls SRC1 or SRC4 pair

Byte 5, bit 4:

0 = CR#_B controls SRC1 pair (default)

1= CR#_B controls SRC4 pair

PCI2 / TME

I/O, SE 33 MHz Clock output/3.3V-tolerance input for enabling Trusted Mode

Sampled at CKPWRGD assertion:

0 = Normal mode, 1 = Trusted mode (no overclocking)

PCI3

O, SE 33 MHz Clock output

PCI4 / GCLK_SEL

I/O, SE 33 MHz Clock output/3.3V-tolerant input for selecting graphic clock source

on pin 20, 21, 24 and 25

Sampled on CKPWRGD assertion;

PCIF0 / ITP_EN

I/O, SE 33 MHz free running clock output/3.3V LVTTL input to enable SRC8 or

CPU2_ITP (sampled on the CKPWRGD assertion)

1 = CPU2_ITP, 0 = SRC8

VSS_PCI

GND

Ground for outputs.

VDD_48

PWR

3.3V power supply for outputs and PLL.

USB_48 / FSA

I/O

Fixed 48 MHz clock output/3.3V-tolerant input for CPU frequency selection

Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.

VSS_48

GND

Ground for outputs.

VDD_IO

PWR

3.3V-1.25V power supply for outputs

SRCT0 / DOT96T

O, DIF True 100 MHz Differential serial reference clocks/Fixed True 96 MHz clock

output. Selected via GCLK_SEL at CKPWRGD assertion

SRCC0 / DOT96C

O, DIF Complementary 100 MHz Differential serial reference clocks/Fixed

complement 96 MHz clock output.

Selected via GCLK_SEL at CKPWRGD assertion

VSS_IO

GND

Ground for outputs.

VDD_PLL3

PWR

3.3V Power supply for PLL3.

SRCT1 /

LCDT_100/27M_NSS

O, DIF,

True 100 MHz differential serial reference clock output/True 100 MHz LCD

video clock output / Non spread 27-MHz video clock output.

Selected via GCLK_SEL at CKPWRGD assertion.

QFN Pin Definitions (continued)

Pin No.

Name

Type

Description

GCLK_SEL

Pin 20

Pin 21

Pin 24

Pin 25

DOT96T DOT96C SRC1T/LCD_100T SRC1C/LCD_100C

SRCT0

SRCC0

27M_NSS

27M_SS

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