CYW43353 datasheet(95/113 Pages) CYPRESS

Part #	CYW43353

Description	Single-Chip 5G MAC/Baseband/Radio with Integrated Bluetooth 4.1 for Automotive and Industrial Applications

PDF	113 Pages

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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95 / 113 page

Document No. 002-14949 Rev. *F

Page 95 of 113

PRELIMINARY

CYW43353

18. Interface Timing and AC Characteristics

18.1 SDIO/gSPI Timing

18.1.1 SDIO Default Mode Timing

SDIO default mode timing is shown by the combination of Figure 32 and Table 44.

Figure 32. SDIO Bus Timing (Default Mode)

Table 44. SDIO Bus Timing1 Parameters (Default Mode)

Timing is based on CL

 40pF load on CMD and Data.

Parameter

Symbol

Minimum

Typical

Maximum

Unit

SDIO CLK (All values are referred to minimum VIH and maximum VIL2)

Min. (Vih) = 0.7 × VDDIO and max (Vil) = 0.2 × VDDIO.

Frequency – Data Transfer mode

fPP

–

MHz

Frequency – Identification mode

fOD

–

400

kHz

Clock low time

tWL

–

Clock high time

tWH

–

Clock rise time

tTLH

–

Clock fall time

tTHL

–

Inputs: CMD, DAT (referenced to CLK)

Input setup time

tISU

5––ns

Input hold time

tIH

5––ns

Outputs: CMD, DAT (referenced to CLK)

Output delay time – Data Transfer mode

tODLY

–

Output delay time – Identification mode

tODLY

–

tWL

tWH

fPP

tTHL

tISU

tTLH

tIH

tODLY

(max)

tODLY

(min)

Input

Output

SDIO_CLK

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