CYW43353 datasheet(96/113 Pages) CYPRESS

Part #	CYW43353

Description	Single-Chip 5G MAC/Baseband/Radio with Integrated Bluetooth 4.1 for Automotive and Industrial Applications

PDF	113 Pages

Scroll/Zoom	100%

Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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96 / 113 page

Document No. 002-14949 Rev. *F

Page 96 of 113

PRELIMINARY

CYW43353

18.1.2 SDIO High-Speed Mode Timing

SDIO high-speed mode timing is shown by the combination of Figure 33 and Table 45.

Figure 33. SDIO Bus Timing (High-Speed Mode)

Table 45. SDIO Bus Timing1 Parameters (High-Speed Mode)

Timing is based on CL

 40pF load on CMD and Data.

Parameter

Symbol

Minimum

Typical

Maximum

Unit

SDIO CLK (all values are referred to minimum VIH and maximum VIL2)

Min. (Vih) = 0.7 × VDDIO and max (Vil) = 0.2 × VDDIO.

Frequency – Data Transfer Mode

fPP

–

MHz

Frequency – Identification Mode

fOD

–

400

kHz

Clock low time

tWL

7––ns

Clock high time

tWH

7––ns

Clock rise time

tTLH

––3ns

Clock fall time

tTHL

––3ns

Inputs: CMD, DAT (referenced to CLK)

Input setup time

tISU

6––ns

Input hold time

tIH

2––ns

Outputs: CMD, DAT (referenced to CLK)

Output delay time – Data Transfer Mode

tODLY

–

Output hold time

tOH

2.5

–

Total system capacitance (each line)

–

tWL

tWH

fPP

tTHL

tISU

tTLH

tIH

tODLY

Input

Output

50% VDD

tOH

SDIO_CLK

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