S34MS02G2 datasheet(38/74 Pages) CYPRESS

38 / 74 page

Document Number: 002-03238 Rev. *E

Page 38 of 74

S34MS01G2

S34MS02G2

S34MS04G2

5.6

Pin Capacitance

Note:

1. For the stacked devices version the Input is 10 pF x [number of stacked chips] and the Input/Output is 10 pF x [number of stacked chips].

5.7

Program / Erase Characteristics

Notes:

1. Typical program time is defined as the time within which more than 50% of the whole pages are programmed (VCC = 1.8V, 25°C).

2. Copy Back Read and Copy Back Program for a given plane must be between odd address pages or between even address pages for the device to meet the program

time (tPROG) specification. Copy Back Program may not meet this specification when copying from an odd address page (source page) to an even address page

(target page) or from an even address page (source page) to an odd address page (target page).

Table 5.6 Pin Capacitance (TA = 25°C, f=1.0 MHz)

Parameter

Symbol

Test Condition

Min

Max

Unit

Input

CIN

VIN = 0V

—

Input / Output

CIO

VIL = 0V

—

Table 5.7 Program / Erase Characteristics

Parameter

Description

Min

Typ

Max

Unit

Program Time / Multiplane Program Time (2)tPROG

—

300

700

µs

Dummy Busy Time for Multiplane Program (S34MS02G2, S34MS04G2)tDBSY

—0.5

µs

Cache Program short busy time

tCBSYW

—5

tPROG

µs

Number of partial Program Cycles in the same page

Main + Spare

NOP

—

Cycle

Block Erase Time (S34MS01G2)

tBERS

—3

Block Erase Time (S34MS02G2, S34MS04G2)

tBERS

—3.5

Read Cache busy time (S34MS01G2)

tCBSYR

—3

µs

Read Cache busy time (S34MS02G2, S34MS04G2)

tCBSYR

—5

µs

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