S34MS02G2 datasheet(13/74 Pages) CYPRESS

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Document Number: 002-03238 Rev. *E

Page 13 of 74

S34MS01G2

S34MS02G2

S34MS04G2

1.6.3

S34MS04G2

Notes:

1. CAx = Column Address bit.

2. PAx = Page Address bit.

3. PLA0 = Plane Address bit zero.

4. BAx = Block Address bit.

5. Block address concatenated with page address and plane address = actual

page address, also known as the row address.

6. I/O[15:8] are not used during the addressing sequence and should be driven

Low.

For the x8 address bits, the following rules apply:



A0 - A11: column address in the page



A12 - A17: page address in the block



A18: plane address (for multiplane operations) / block

address (for normal operations)



A19 - A29: block address

For the x16 address bits, the following rules apply:



A0 - A10: column address in the page



A11 - A16: page address in the block



A17: plane address (for multiplane operations) / block

address (for normal operations)



A18 - A28: block address

Table 1.5 Address Cycle Map — 4 Gb Device

Bus Cycle

I/O [15:8]

(6)

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

1st / Col. Add. 1

—

A0 (CA0)

A1 (CA1)

A2 (CA2)

A3 (CA3)

A4 (CA4)

A5 (CA5)

A6 (CA6)

A7 (CA7)

2nd / Col. Add. 2

—

A8 (CA8)

A9 (CA9)

A10 (CA10)

A11 (CA11)

Low

3rd / Row Add. 1

—

A12 (PA0)

A13 (PA1)

A14 (PA2)

A15 (PA3)

A16 (PA4)

A17 (PA5)

A18 (PLA0)

A19 (BA0)

4th / Row Add. 2

—

A20 (BA1)

A21 (BA2)

A22 (BA3)

A23 (BA4)

A24 (BA5)

A25 (BA6)

A26 (BA7)

A27 (BA8)

5th / Row Add. 3

—

A28 (BA9)

A29 (BA10)

Low

x16

1st / Col. Add. 1

Low

A0 (CA0)

A1 (CA1)

A2 (CA2)

A3 (CA3)

A4 (CA4)

A5 (CA5)

A6 (CA6)

A7 (CA7)

2nd / Col. Add. 2

Low

A8 (CA8)

A9 (CA9)

A10 (CA10)

Low

3rd / Row Add. 1

Low

A11 (PA0)

A12 (PA1)

A13 (PA2)

A14 (PA3)

A15 (PA4)

A16 (PA5)

A17 (PLA0)

A18 (BA0)

4th / Row Add. 2

Low

A19 (BA1)

A20 (BA2)

A21 (BA3)

A22 (BA4)

A23 (BA5)

A24 (BA6)

A25 (BA7)

A26 (BA8)

5th / Row Add. 3

Low

A27 (BA9)

A28 (BA10)

Low

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