MSP3410B datasheet(13/68 Pages) MICRONAS

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PRELIMINARY DATA SHEET

MSP 3410 B

ITT Semiconductors

5. Control Bus Interface

As a slave receiver, the MSP 3410 B can be controlled

via I2C bus. Access to internal memory locations is

achieved by subaddressing. The FP processor and the

DFP processor parts have two separate subaddressing

In order to allow for more MSP 3410 B IC’s to be con-

nected to the control bus, an ADR_SEL pin has been im-

plemented. With ADR_SEL pulled to high, the MSP

3410 B responds to changed device addresses, thus

two identical devices can be selected. Other devices of

the same family will have different subaddresses (e.g.

34X0).

By means of the RESET bit in the CONTROL register all

devices with the same device address are reset.

The IC is selected by asserting a special device address

in the address part of a I2C transmission. A device ad-

dress pair is defined as a write address (80 hex or 84

hex) and a read address (81 hex or 85 hex). Writing is

done by sending the device write address first, followed

by the subaddress byte, two address bytes, and two

data bytes. For reading, the read address has to be

transmitted first by sending the device write address (80

hex or 84 hex) followed by the subaddress byte and two

address bytes. Without sending a stop condition, read-

ing of the addressed data is done by sending the device

read address (81 hex or 85 hex) and reading two bytes

of data. Refer to Fig. 5–1: I2C Bus Protocol and section

5.2. Proposal for MSP 3410 B I2C Telegrams.

Due to the internal architecture of the MSP 3410 B, the

IC cannot react immediately to an I2C request. The typi-

cal response time is about 0.3 ms for the DFP processor

part and 1 ms for the FP processor part if NICAM proces-

sing is active. If the receiver (MSP) can’t receive another

complete byte of data until it has performed some other

functions, for example servicing an internal interrupt, it

can hold the clock line I2C_CL LOW to force the trans-

mitter into a wait state. The positions within a transmis-

sion where this may happen are indicated by ’Wait’ in

section 5.1. The maximum Wait-period of the MSP dur-

ing normal operation mode is less than 7 ms.

I2C-Bus error conditions (valid only from TC17 on):

In case of any internal error, the MSPs wait-period is ex-

tended to 7.07 ms. Afterwards the MSP does not ac-

knowledge (NAK) the device address. The data line will

be left HIGH by the MSP and the clock line will be re-

leased. The master can then generate a STOP condition

to abort the transfer.

By means of NAK, the master is able to recognize the er-

ror state and to reset the IC via I2C-Bus. While transmit-

ting the reset protocoll (s. 5.2.4.) to ‘CONTROL’, the

master must ignore the not acknowledge bits (NAK) of

the MSP.

Table 5–1: I2C Bus Device and Subaddresses

Name

Binary Value

Hex Value

Mode

Function

ADR_SEL=low

ADR_SEL=high

MSP

1000 000x

80/81

84/85

R/W

MSP device address

CONTROL

0000 0000

software reset

TEST

0000 0001

only for internal use

WR_FP

0001 0000

write address FP

RD_FP

0001 0001

read address FP

WR_DFP

0001 0010

write address DFP

RD_DFP

0001 0011

read address DFP

Table 5–2: Control Register

Name

MSB

13..1

LSB

CONTROL

RESET

MSP3410B Datasheet(PDF) 13 Page - Micronas

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