06 | Keysight | Infiniium DCA-X 86100D Wide-Bandwidth Oscilloscope Mainframe and Modules - Data Sheet

Mainframe specifications (Continued)

86100D with option STR

86100D with option ETR or with options ETR + PTB

External divided trigger (AC coupled) Not available with option STR

Input frequency range

N/A

50 MHz - 13 GHz (effective divide by 2)

50 MHz - 15 GHz (characteristic)

Option PTB: 50 MHz - 32 GHz (effective divide by 1)

Pattern lock frequency range

N/A

50 MHz - 13 GHz

50 MHz - 15 GHz (characteristic)

Option PTB: 50 MHz - 32 GHz

Pattern lock pattern length range

N/A

1 to 2^23 UI in Scope and Eye/Mask Modes

1 to 2^16 UI in Jitter Mode

Trigger sensitivity

N/A

Slew rate > 2 V/ns:

200 mVpp

Maximum input signal

N/A

Max Trigger input: 2 Vpp

Option PTB: Max PTB Input: 1.3 Vpp with DC offset up

to + 200 mV

System jitter

N/A

Tested at 10 GHz, 200 mVpp

1.2 ps rms for time delays less than 100 ns, (Maximum)

750 fs rms at minimum delay setting, (characteristic)

Option PTB when PTB is enabled:

2.4 GHz, 750 mVpp

≤ 200 fs (characteristic)

< 400 fs, with 54XXX, 8348X, or N1045A (non Option

LOJ) module (characteristic)

750 mVpp

≤ 120 fs (characteristic)

< 400 fs, with 54XXX, 8348X, or N1045A (non Option

LOJ) module (characteristic)

20, and 40 GHz, 500 mVpp

≤ 90 fs (characteristic)

< 200 fs, with 54XXX, 8348X, or N1045A

(non Option LOJ) module(characteristic)

Inputs

Trigger input connector

Trigger input nominal impedance

50Ω

50 Ω

Option PTB: PTB input: 50 Ω

Specifications (Continued)

1. The internal precision timebase works with typical digital clock signals, such as a BERT output, as well as sine waves. If the rise time or fall time of the

clock signal is less than 15% of the period of the clock (for example, less than 15 ps for a 10 GHz clock), reduce the edge speed by using an external

low-pass filter. or length of cable. For the lowest jitter, use a signal that is as close as possible to the maximum signal amplitude (1.3 Vpp) and minimize any

sub-harmonics.

2. High Sensitivity Hysteresis mode improves the high frequency trigger sensitivity but is not recommended when using noisy, low frequency signals that may

result in false triggers without normal hysteresis enabled.

3. Module triggering enables precision waveform analyzer modules (86108), clock recovery modules (83496) and TDR modules to be used as a trigger source.

Without support for module triggering, external connections between the module and the mainframe may be required.

4. 86100D mainframes ship with a 2.92mm (f) to (f) adapter for this port.