S818 datasheet(7/23 Pages) SII

7 / 23 page

Rev.1.2

LOW DROPOUT CMOS VOLTAGE REGULATOR

S-818 Series

Seiko Instruments Inc.

Operation

1. Basic operation

Figure 7 shows the block diagram of the S-818

Series.

The error amplifier compares a reference voltage

VREF with the part of the output voltage divided by the

feedback resistors Rs and Rf. It supplies the output

transistor with the gate voltage, necessary to ensure

certain output voltage free of any fluctuations of input

voltage and temperature.

2. Output transistor

The S-818 Series uses a low on-resistance Pch MOS FET as the output transistor.

Be sure that VOUT does not exceed VIN+0.3 V to prevent the voltage regulator from being broken due to

inverse current flowing from VOUT pin to VIN pin through the parasitic diode.

3. Power Off Pin (ON/OFF Pin)

This pin activates and inactivates the regulator.

When the ON/OFF pin is switched to the power off level, the operation of all internal circuit stops, the built-in

Pch MOSFET output transistor between VIN and VOUT pin is switched off, suppressing current consumption.

The VOUT pin goes to the Vss level due to internal divided resistance of several M

Ω between VOUT pin and

VSS pin.

The structure of the ON/OFF pin is shown in Figure 8. Since the ON/OFF pin is neither pulled down nor pulled

up internally, do not keep it in the floating state. Current consumption increases if a voltage of 0.3 V to VIN-0.3

V is applied to the ON/OFF pin. When the power off pin is not used, connect it to the VIN pin for product type

"A" and to the VSS pin for product type "B".

Table 6 Power off pin function by product type

Product

type

ON/OFF pin

Internal

circuit

VOUT pin

voltage

Current

consumption

“H” : Power on

Operating

Set value

Iss1

“L” : Power off

Stop

VSS level

Iss2

“H” : Power off

Stop

VSS level

Iss2

“L” : Power on

Operating

Set value

Iss1

Reference

voltage

circuit

VOUT

*1 Parasitic diode

VSS

VIN

Error amplifier

Current

source

Vref

ON/OFF

VIN

VSS

Figure 8 ON/OFF Pin

Figure 7 Typical Circuit Block Diagram

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