ADP3166 datasheet(15/20 Pages) AD

15 / 20 page

REV. 0

ADP3166

–15–

Ramp Resistor Selection

The ramp resistor (RR) is used for setting the size of the internal

PWM ramp. The value of this resistor is chosen to provide the

best combination of thermal balance, stability, and transient

response. The following expression is used for determining the

optimum value:

600 nH

.mW

DDS

××

354 2

381

Ω

(19)

where AR is the internal ramp amplifier gain, AD is the current

balancing amplifier gain, RDS is the total low-side MOSFET on

resistance, and CR is the internal ramp capacitor value. The

closest standard 1% resistor value is 383 k

Ω.

The internal ramp voltage magnitude can be calculated using

A– D

.– .

. V

kpF

kHz

VID

()×

××

()×

××

1 0 125

383

330

041

Ω

(20)

The size of the internal ramp can be made larger or smaller. If it

is made larger, stability and transient response will improve, but

thermal balance will degrade. Conversely, if the ramp is made

smaller, thermal balance will improve at the sacrifice of transient

response and stability. The factor of three in the denominator of

Equation 19 sets a ramp size that gives an optimal balance for

good stability, transient response, and thermal balance.

COMP Pin Ramp

There is a ramp signal on the COMP pin due to the droop

voltage and output voltage ramps. This ramp amplitude adds to

the internal ramp to produce the following overall ramp signal

at the PWM input.

–

R+ R

– nD

OOD

()×()

××













(21)

For this example, the overall ramp signal is found to be 0.48 V.

Current Limit Set Point

To select the current limit set point, we need to find the resistor

value for RLIM. The current limit threshold for the ADP3166 is

set with a 3 V source (VLIM) across RLIM with a gain of 10.4 mV/

µA

(ALIM). RLIM can be found using the following:

LIM

(22)

For values of RLIM greater than 500 k

Ω, the current limit may be

lower than expected, so some adjustment of RLIM may be needed.

Here, ILIM is the average current limit for the output of the sup-

ply. For our example, choosing 75 A for ILIM, we find RLIM to be

378 k

Ω, for which we choose 374 kΩ as the nearest 1% value.

The per phase current limit described earlier has its limit deter-

mined by the following:

V– V – V

–

PHLIM

COMP(MAX)

BIAS

DS(MAX)

≅

(23)

For the ADP3166, the maximum COMP voltage (VCOMP(MAX))

is 3.3 V, the COMP pin bias voltage (VBIAS) is 1.2 V, and the

current balancing amplifier gain (AD) is 5. Using VR of 0.48 V,

and RDS(MAX) of 4.2 m

Ω (low-side on resistance at 150°C), we

find a per phase limit of 74 A.

This limit can be adjusted by changing the ramp voltage VR. But

make sure not to set the per phase limit lower than the average

per phase current (ILIM/n).

There is also a per phase initial duty cycle limit determined by:

D= D

V–V

MAX

COMP MAX

BIAS

()

(24)

For this example, the maximum duty cycle is found to be 0.55.

Feedback Loop Compensation Design

Optimized compensation of the ADP3166 allows the best pos-

sible response of the regulator’s output to a load change. The

basis for determining the optimum compensation is to make the

regulator and output decoupling appear as an output impedance

that is optimized over the widest possible frequency range,

including dc, and equal to the droop resistances (RO and

ROD). With the output impedance, the output voltage will respond

in proportion with the load current; this ensures the optimal

output positioning and allows the minimization of the output

decoupling.

With the multimode feedback structure of the ADP3166, one

needs to set the feedback compensation to make the converter’s

output impedance work in parallel with the output decoupling to

meet this goal. There are several poles and zeros created by the

output inductor and decoupling capacitors (output filter) that

need to be compensated for.

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