MP4027 – PRIMARY-SIDE CONTROL, OFFLINE LED CONTROLLER WITH ACTIVE PFC

MP4027 Rev. 1.02

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11

12/9/2014

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(typical 0.413V);

sensing

resistor

connected

between the MOSFET source and GND.

Power-Factor Correction (PFC)

MULT is connected to a pull-up resistor from

the rectified-instantaneous-line voltage; the

multiplier output is sinusoidal. This signal sets

the sinusoidal primary side peak current. This

achieves a high power factor (PF).

Inductor current

Multiplier output

Figure 4: Power-Factor Correction

The maximum output voltage of the multiplier is

clamped to 2.0V, setting the cycle-by-cycle

current limit.

VCC Under-Voltage Lockout (UVLO)

When the VCC voltage drops below the UVLO

threshold 9.5V, the IC stops switching and

shuts down; the operating current is very low

under this condition. VCC is then charged by

the external resistor from the AC line. Figure 5

shows the typical waveform of UVLO.

Figure 5: VCC Under-Voltage Lockout

Auto Starter

The MP4027 integrates an auto-restart that

begins timing when the MOSFET turns off. If

ZCD fails to send a turn-on signal after 190µs, a

turn-on signal is initiated. This avoids an

unnecessary IC shut down if ZCD misses

detection.

Minimum Off Time

The MP4027 operates with variable switching

frequency. The frequency changes with the

input instantaneous line voltage. To limit the

maximum

frequency

and

enhance

EMI

performance, the chip employs an internal

minimum OFF-time of 5.5µs.

Leading-Edge Blanking (LEB)

Internal

leading-edge-blanking

(LEB)

is

employed to prevent a switching pulse from

terminating

prematurely

due

to

parasitic

capacitance discharging when the MOSFET

turns on. During the blanking time, the path

from CS/ZCD to the current comparator input is

blocked. Figure 6 shows the leading-edge

blanking time. The LEB time of primary-side

OCP detection is relatively short at 280ns.

t

V

CS

t

Figure 6: Leading-Edge Blanking

Output Over-Voltage Protection (OVP)

Output

over-voltage

protection

prevents

component

damage

from

over-voltage

conditions.

The auxiliary winding’s positive

plateau voltage is proportional to the output

voltage; the OVP uses the auxiliary-winding

voltage instead of directly monitoring the output

voltage.

Figure 7 shows the OVP circuit. Once the ZCD

voltage is higher than 5.1V and exceeds the

OVP blanking time (during the gate turn-off

interval), the OVP signal is latched, turning the

gate driver off. When VCC drops below UVLO,

the IC restarts.