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LTC3622 Datasheet(PDF) 13 Page - Linear Technology |
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LTC3622 Datasheet(HTML) 13 Page - Linear Technology |
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13 / 24 page ![]() LTC3622/ LTC3622-2/LTC3622-23/5 13 3622fc For more information www.linear.com/LTC3622 APPLICATIONS INFORMATION at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the VIN input. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at VIN large enough to damage the part. When choosing the input and output ceramic capacitors, choose the X5R and X7R dielectric formulations. These dielectrics have the best temperature and voltage char- acteristics of all the ceramics for a given value and size. Since the ESR of a ceramic capacitor is so low, the input and output capacitor must instead fulfill a charge storage requirement.Duringaloadstep,theoutputcapacitormust instantaneously supply the current to support the load until the feedback loop raises the switch current enough to support the load. Typically, five cycles are required to respond to a load step, but only in the first cycle does the output voltage drop linearly. The output droop, VDROOP, is usually about three times the linear drop of the first cycle. Thus, a good place to start with the output capacitor value is approximately: COUT = 3 ΔIOUT ƒO • VDROOP More capacitance may be required depending on the duty cycle and load step requirements. In most applications, the input capacitor is merely required to supply high frequency bypassing, since the impedance to the supply is very low. A 10µF ceramic capacitor is usually enough for these conditions. Place this input capacitor as close to the VIN1 and VIN2 pins as possible. Output Power Good When the LTC3622’s output voltages are within the ±7.5% windowoftheregulationpoint,theoutputvoltagesaregood andthePGOODpinsarepulledhighwithexternalresistors. Otherwise, internal open-drain pull-down devices (275Ω) willpullthePGOODpinslow.TopreventunwantedPGOOD glitches during transients or dynamic VOUT changes, the LTC3622’s PGOOD falling edge includes a blanking delay of approximately 32 switching cycles. Frequency Synchronization Capability The LTC3622 has the capability to synchronize to a ±50% range of the internal programmed frequency. It takes several cycles of external clock to engage the sync mode, and roughly 2μs for the part to detect the absence of the external clock signal. Once engaged in sync, the LTC3622 immediately runs at the external clock frequency. Inductor Selection Given the desired input and output voltages, the inductor valueandoperatingfrequencydeterminetheripplecurrent: ΔIL= VOUT ƒ •L 1– VOUT VIN(MAX) Lower ripple current reduces power losses in the inductor, ESR losses in the output capacitors and output voltage ripple. Highest efficiency operation is obtained at low frequency with small ripple current. However, achieving this requires a large inductor. There is a trade-off between component size, efficiency and operating frequency. A reasonable starting point is to choose a ripple current that is about 50% of IOUT(MAX). To guarantee that ripple current does not exceed a specified maximum, the induc- tance should be chosen according to: L = VOUT ƒ • ΔIL(MAX) 1– VOUT VIN(MAX) Once the value for L is known, the type of inductor must be selected. Actual core loss is independent of core size for a fixed inductor value, but is very dependent on the inductance selected. As the inductance or frequency in- creases, core loss decreases. Unfortunately, increased inductance requires more turns of wire and therefore copper losses increase. Ferrite designs have very low core losses and are pre- ferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates “hard,” which means that inductancecollapsesabruptlywhenthepeakdesigncurrent is exceeded. This results in an abrupt increase in inductor |
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