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LT8584

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Figure 9. Internal Switch Voltage Waveform

The RMS input current can be increased by increasing

the ratio between the effective switch on-time, tON, and

off-time, tOFF. This off-time ratio is set by the transformer

ratio, N. The following equation sets the switch off-time

to approximately 1/3 of the switch on-time to optimize

power transfer and efficiency.

Secondary Turns

Primary Turns

VMODULE

3 • VIN

The off-time ratio should not be decreased much beyond

1/5; otherwise, secondary-side energy transfer time be-

comes too short, and the converter efficiency is reduced.

Some applications may require a lower RMS current due

to charging limitations or thermal dissipation limitations.

Both can be reduced by increasing the turns ratio, N. Use

the following equation to size the transformer’s primary

inductance:

LPRI =

IPK • ƒBM •

VIN

VMODULE













Keep the primary inductance in the range of 2.2µH to

10µH. The lower limit guarantees proper detection of an

open circuit in the transformer’s secondary. The upper

limit guarantees the high-impedance detector does not

activate a false switch error during normal operation.

Leakage Inductance

Leakage inductance causes added voltage stress on the

internal power NPN collector. The LT8584 uses an internal

Zenerclamptoabsorbthisleakagespikeenergyandclamp

the switch node voltage to 50V. The leakage spike energy

should be limited to improve efficiency. Figure 9 shows

the waveform of the internal NPN switch.

Design the transformer to have minimum leakage induc-

tance. Keep both transformer windings tightly wound

around the core air gap. Using a bifilar winding or a

sandwiched secondary decreases leakage inductance.

Note that increased interwinding capacitance is a trade-off

with lower leakage inductance. Several iterations may be

required to optimize the transformer design.

Higher transformer turns ratios benefit from higher

reflected capacitance that helps snub the leakage spike.

N ratios less than 8 usually require an RCD snubber to

help clamp this primary-side leakage spike and increase

the converter efficiency. Good values for the resistor and

capacitor are 4.99kΩ and 22nF, respectively.

Output Diode

The output diode(s) are selected based on the maximum

repetitive reverse voltage (VRRM) and the average forward

current, IF(AVG). The output diode’s VRRM should at a mini-

mum exceed VMODULE + N • VVIN. The LT8584’s internal

OVP circuitry triggers at 50V, and VRRM should therefore

exceed N•(50 + VVIN) to prevent damage to the output

diode during an OVP event. Note that the leakage spike

will usually cause the OVP to trigger roughly 10% lower

than the nominal reflected voltage on the primary. The

output diode’s IF(AVG) should exceed IPK/2N, the average

short-circuit current. The average diode current is also a

function of the output voltage.

IF(AVG) =

IPK • VVIN

2 • VMODULE +N • VVIN

(

)

The highest average diode current occurs at low output

voltages and decreases as the output voltage increases.

Reverse recovery time, reverse bias leakage, and junc-

tion capacitance should also be considered. All affect

the overall charging efficiency. Excessive diode reverse

recovery times can cause appreciable discharging of the

outputstack,therebydecreasingchargerecovery.Choose

a diode with a reverse recovery time of less than 75ns.

8584 F06

VSW

VVIN + VSTACK/N

MUST BE LESS THAN 40V

LEAKAGE

SPIKE CLAMPED

TO 50V

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