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LTC3351 Datasheet(PDF) 39 Page - Linear Technology

Part # LTC3351
Description  Hot Swappable Supercapacitor Charger, Backup Controller and System Monitor
PDF  56 Pages
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LTC3351 Datasheet(HTML) 39 Page - Linear Technology

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LTC3351
39
3351f
For more information www.linear.com/LTC3351
APPLICATIONS INFORMATION
Higher shunt current may be accommodated with an ex-
ternal NMOS and resistor across each capacitor as shown
in Figure 13. The shunt current will be VSHUNT divided by
Rx (assuming the RDS(ON) of MNx is small compared to
Rx). The logic level NMOS must be selected so that its
VGS at the desired shunt current is less than one half the
VSHUNTvoltage.Whenusingthiscircuittheshuntresistors
should be increased to 10Ω to minimize the drop across
the LTC3351’s internal shunt FET and thus maximize the
VGS for MNx. Using 10Ω resistors will also reduce the
power dissipation allowing a smaller package size com-
pared to the typical application’s 2.7Ω. When using 10Ω
resistors the internal shunt FET will turn on the external
NMOS, however the internal balancer’s current will not
create enough voltage across the 10Ω resistors to turn
on the external NMOS. Additionally, increasing the 10Ω
resistors to 500Ω will allow the internal balancers to turn
on the external FETs, thus also increasing balance current.
Input Short Protection
TheLTC3351’sinputcurrentsenseamplifier,ISNSP_HSto
ISNSM and ISNSP_CHG to can have at most 0.3V between
them. This is not typically an issue since the LTC3351
regulates input current to 48mV (hot swap current limit)
or 32mV (charger input current limit) using these pins.
The LTC3351 hot swap does not regulate reverse input
current. If the input voltage is rapidly reduced (the input
directly shorted to ground for instance) large currents
will flow from the VOUT capacitance to the VIN short.
Unless external protection is used, these large currents
can quickly produce many volts of drop across the input
sense resistor(s), overstressing the input current sense
pins. If the input is shorted after it has fallen below the
UV threshold, this is not an issue since the hot swap FETs
have already been turned off. However, if the input supply
can be shorted to ground while the LTC3351 is connected,
the input protection circuit in Figure 14 is recommended.
Also if the system load is so low that the LTC3351 circuit
can be disconnected from the input and then shorted to
ground before the input falls below UV, then the same
circuit is also recommended.
Figure 14.
LTC3351
ISNSP_X
1
ISNSM
VOUT
VIN
3351 F14
ISNSP_X
1
1
Input Short Protection Circuit
Since there are several possible configurations for the
input current sense resistors, not all possible protection
circuits are shown. To construct a circuit for another con-
figuration of input current sense resistors, there should
be one Schottky diode for each current sense ampli-
fier (ISNSP_HS-ISNSM and ISNSP_CHG-ISNSM). There
should be 1Ω between the current sense resistor and the
current sense pins, and the diode should be connected
such that it can conduct current in the direction from VOUT
to VIN, this means the anodes will be connected to ISNSM.
In this circuit, the Schottky diode is a simple clamp to limit
the voltage across the pins. The 1Ω resistors are needed
to limit the current in each Schottky diode. Clearly, if only
one sense resistor is used, only one protection diode is
needed.
Supercapacitor Settling
The ESR-only supercapacitor model using a capacitor in
series with an equivalent series resistance (ESR) is over-
simplified.Realsupercapacitorshaveanadditionalsettling
time due to their internal physics
To explain the implications of this settling, assume a super
capacitor of infinite capacitance such that any voltage
change due to charging or discharging can be ignored. In
thesimpleESR-onlymodel,apulseofcurrentwouldsimply
result in a step in voltage at its rising edge and a step back
to its initial voltage at its falling edge. A real supercapaci-
tor’s response to the same pulse of current’s rising edge
will be an instantaneous step in voltage due to the high
frequency ESR, followed by a settling to a higher voltage
due to the “DC” ESR. On the falling edge there will be an



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