THCV213-214_Rev.2.40_E

Copyright©2014 THine Electronics, Inc.

THine Electronics, Inc.

4/19

THCV214 Pin Description

PIN Name

PIN No

Type

Description

RXIN-, RXIN+

41, 42

LVDSIN

LVDS input.

D17-D0

8, 9, 10, 11, 13,

14, 15, 16, 17,

19, 20, 21, 22,

23, 25, 26, 27, 28

OUT

Data outputs.

SYNC0-SYNC2

32, 33, 34

OUT

Sync output.

DE

31

OUT

Data Enable (DE) output.

CLKOUT

6

OUT

Clock output.

LOCKN

36

OUT

Lock detects output.

H: Unlock, L: Lock.

Can be used as an input signal detector, too.

PDWN

3

IN

H: Normal operation.

L: Power Down, all outputs except LOCKN and

CLKOUT are held low. Refer to Fig9 for details.

(Note1)

EDGE

38

IN

Output clock triggering edge select.

H: Rise edge, L: Fall edge.

OE

39

IN

Output Enable.

(DE, SYNC0-SYNC2, D0-D17,CLKOUT)

H: Output disabled, all outputs are Hi-Z.

L: Output enabled. (Note1)

MODE1, MOD0

1, 2

IN

Select operation mode.

Both must be tied to GND.

MOD0

MOD1

L

L

Normal Mode

Shake Hand Mode

Others

Not Available

RESERVED0

4

IN

Must be tied to GND.

RESERVED1

45

IN

Must be tied to LVDSGND.

RESERVED2

46

IN

Must be tied to LVDSGND.

VDD

35

Power

Power supply pin for digital circuitry.

GND

30, 37

Power

Ground pins for digital circuitry.

LVDSVDD

44

Power

Power supply pin for LVDS input.

LVDSGND

40,43

Power

Ground pins for LVDS input.

PLLVDD

48

Power

Power supply pin for PLL circuitry.

PLLGND

47

Power

Ground pin for PLL circuitry.

VDDO

5, 12, 24

Power

Power supply pins for TTL output.

GNDO

7, 18, 29

Power

Ground pins for TTL output.

Note1: The state of outputs determined by the combination of OE and PDWN is as follow.