LTC3883 datasheet(13/22 Pages) LINER

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LTC3870

3870fb

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and control power to be derived from other high efficiency

sources such as +5V or +12V rails in the system. Using

EXTVCC can significantly reduce the IC temperature in

high VIN applications. Tying the EXTVCC pin to a 5V supply

reduces the junction temperature in the previous example

from 125°C to: TJ = 70°C + (34mA) (5V) (43°C/W) = 77°C.

Do not apply more than 14V to the EXTVCC pin.

For applications where the main input power is 5V, tie

the VIN and INTVCC pins together and tie the combined

pins to the 5V input with a 1Ω or 2.2Ω resistor as shown

in Figure 2 to minimize the voltage drop caused by the

gate charge current. This will override the INTVCC linear

regulator and will prevent INTVCC from dropping too low

due to the dropout voltage. Make sure the INTVCC voltage

is at or exceeds the RDS(ON) test voltage for the MOSFET

which is typically 4.5V for logic-level devices.

applicaTions inForMaTion

the final arbiter is the total input current for the regulator.

If a change is made and the input current decreases, then

the efficiency has improved. If there is no change in input

current, then there is no change in efficiency.

Undervoltage Lockout

TheLTC3870hasaprecisionUVLOcomparatorconstantly

monitoring the INTVCC voltage to ensure that an adequate

gate-drive voltage is present. It locks out the switching

action and pulls down RUN pins when INTVCC is below

3.7V. To prevent oscillation when there is a disturbance on

the INTVCC, the UVLO comparator has 300mV of precision

hysteresis. In multiphase operation, when LTC3870 is in

undervoltage lockout, the RUN0 and RUN1 pins are pulled

down to disable the master’s switching action.

Phase-Locked Loop and Frequency Synchronization

The LTC3870 has a phase-locked loop (PLL) comprised

of an internal voltage-controlled oscillator (VCO) and a

phase detector. This allows the internal clock to be locked

to the falling edge of an external clock signal applied to

the SYNC pin. The turn-on of channel 0/channel 1’s top

MOSFET is synchronized or out-of-phase with the falling

edge of the external clock. The phase detector is an edge

sensitive digital type that provides zero degree phase shift

between the external and internal oscillators. This type of

phase detector does not exhibit false lock to harmonics

of the external clock.

Theoutputofthephasedetectorisapairofcomplementary

current sources that charge or discharge the internal filter

network.Thereisaprecision10µAofcurrentflowingoutof

the FREQ pin. This allows the user to use a single resistor

to SGND to set the switching frequency when no external

clock is applied to the SYNC pin. The voltage on the FREQ

pin is equal to the resistance multiplied by 10µA current

(e.g. the voltage is 1V with a 100k resistor from the FREQ

pin to SGND). The internal switch between FREQ pin and

the integrated PLL filter network is ON, allowing the filter

network to be pre-charged to the same voltage potential

as the FREQ pin. The relationship between the voltage

on the FREQ pin and the operating frequency is shown

in Figure 3 and specified in the Electrical Characteristic

table. If an external clock is detected on the SYNC pin, the

internal switch mentioned above will turn off and isolate

3870 F04

VIN

CIN

CINTVCC

4.7µF

RVIN

INTVCC

LTC3870

Figure 2. Setup for a 5V Input

Topside MOSFET Driver Supply (CB, DB)

External bootstrap capacitor CB, connected to the BOOST

pin, supplies the gate drive voltages for the topside MOS-

FET. Capacitor CB in the Functional Diagram is charged

though external diode DB from INTVCC when the SW pin

is low. When the topside MOSFET is to be turned on, the

driver places the CB voltage across the gate source of the

MOSFET. This enhances the MOSFET and turns on the

topside switch. The switch node voltage, SW, rises to VIN

and the BOOST pin follows. With the topside MOSFET on,

the boost voltage is above the input supply:

VBOOST = VIN + VINTVCC – VDB

The value of the boost capacitor, CB, needs to be 100 times

thatofthetotalinputcapacitanceofthetopsideMOSFET(s).

ThereversebreakdownoftheexternalSchottkydiodemust

begreaterthanVIN(MAX).Whenadjustingthegatedrivelevel,

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