LTC3859AL datasheet(16/38 Pages) LINER

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LTC3899

3899fa

For more information www.linear.com/LTC3899

OPERATION (Refer to the Functional Diagrams)

for the boost) even though the voltage on the ITH pin

indicates a lower value. If the average inductor current is

higher than the load current, the error amplifier, EA, will

decrease the voltage on the ITH pin. When the ITH volt-

age drops below 0.425V, the internal sleep signal goes

high (enabling sleep mode) and both external MOSFETs

are turned off. The ITH pin is then disconnected from the

output of the EA and parked at 0.450V.

In sleep mode, much of the internal circuitry is turned off,

reducing the quiescent current that the LTC3899 draws.

If one channel is in sleep mode and the other two are

shut down, the LTC3899 draws only 29μA of quiescent

current (with DRVSET = 0V). If two channels are in sleep

mode and the other shut down, it draws only 34μA of

quiescent current. If all three controllers are enabled in

sleep mode, the LTC3899 draws only 39μA of quiescent

current. In sleep mode, the load current is supplied by

the output capacitor. As the output voltage decreases,

the EA’s output begins to rise. When the output voltage

drops enough, the ITH pin is reconnected to the output

of the EA, the sleep signal goes low, and the controller

resumes normal operation by turning on the top external

MOSFET (the bottom external MOSFET for the boost) on

the next cycle of the internal oscillator.

When a controller is enabled for Burst Mode operation,

the inductor current is not allowed to reverse. The reverse

current comparator (IR) turns off the bottom external

MOSFET (the top external MOSFET for the boost) just

before the inductor current reaches zero, preventing it

from reversing and going negative. Thus, the controller

operates discontinuously.

In forced continuous operation, the inductor current is

allowed to reverse at light loads or under large transient

conditions. The peak inductor current is determined by

the voltage on the ITH pin, just as in normal operation.

In this mode, the efficiency at light loads is lower than in

Burst Mode operation. However, continuous operation

has the advantage of lower output voltage ripple and

less interference to audio circuitry. In forced continuous

mode, the output ripple is independent of load current.

Clocking the LTC3899 from an external source enables

forced continuous mode (see the Frequency Selection

and Phase-Locked Loop section).

WhenthePLLIN/MODEpinisconnectedforpulse-skipping

mode,theLTC3899operatesinPWMpulse-skippingmode

at light loads. In this mode, constant frequency operation

is maintained down to approximately 1% of designed

maximum output current. At very light loads, the current

comparator, ICMP, may remain tripped for several cycles

and force the external top MOSFET (bottom for the boost)

to stay off for the same number of cycles (i.e., skipping

pulses).Theinductorcurrentisnotallowedtoreverse(dis-

continuous operation). This mode, like forced continuous

operation, exhibits low output ripple as well as low audio

noise and reduced RF interference as compared to Burst

Mode operation. It provides higher low current efficiency

than forced continuous mode, but not nearly as high as

Burst Mode operation.

Frequency Selection and Phase-Locked Loop

(FREQ and PLLIN/MODE Pins)

Theselectionofswitchingfrequencyisatrade-offbetween

efficiency and component size. Low frequency opera-

tion increases efficiency by reducing MOSFET switching

losses, but requires larger inductance and/or capacitance

to maintain low output ripple voltage.

The switching frequency of the LTC3899’s controllers can

be selected using the FREQ pin.

If the PLLIN/MODE pin is not being driven by an external

clock source, the FREQ pin can be tied to GND, tied to

INTVCCorprogrammedthroughanexternalresistor.Tying

FREQ to GND selects 350kHz while tying FREQ to INTVCC

selects 535kHz. Placing a resistor between FREQ and GND

allows the frequency to be programmed between 50kHz

and 900kHz, as shown in Figure 10.

A phase-locked loop (PLL) is available on the LTC3899

to synchronize the internal oscillator to an external clock

source that is connected to the PLLIN/MODE pin. The

LTC3899’s phase detector adjusts the voltage (through an

internal lowpass filter) of the VCO input to align the turn-

on of controller 1’s external top MOSFET (and controller

3’s external bottom MOSFET) to the rising edge of the

synchronizing signal. Thus, the turn-on of controller 2’s

external top MOSFET is 180° out of phase to the rising

edge of the external clock source.

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