ISL6526AEVAL2 datasheet(11/18 Pages) RENESAS

11 / 18 page

ISL6526, ISL6526A

FN9055 Rev 12.00

Page 11 of 18

Sep 30, 2015

and COMP pins. The feedback resistors for both regulators

should also be located as close as possible to the relevant

FB pin with vias tied straight to the ground plane as required.

Feedback Compensation

Figure 5 highlights the voltage-mode control loop for a

synchronous-rectified buck converter. The output voltage

(VOUT) is regulated to the Reference voltage level. The

error amplifier (Error Amp) output (VE/A) is compared with

the oscillator (OSC) triangular wave to provide a pulse

width modulated (PWM) wave with an amplitude of VIN at

the PHASE node. The PWM wave is smoothed by the output

filter (LO and CO).

The modulator transfer function is the small-signal transfer

function of VOUT/VE/A. This function is dominated by a DC

Gain and the output filter (LO and CO), with a double pole

break frequency at fLC and a zero at fESR. The DC Gain of

the modulator is simply the input voltage (VIN) divided by the

peak-to-peak oscillator voltage

VOSC.

Modulator Break Frequency Equations

The compensation network consists of the error amplifier

(internal to the ISL6526, ISL6526A) and the impedance

networks ZIN and ZFB. The goal of the compensation

network is to provide a closed loop transfer function with the

highest 0dB crossing frequency (f0dB) and adequate phase

margin. Phase margin is the difference between the closed

loop phase at f0dB and 180°. Equations 6, 7, 8 and 9 relate

the compensation network’s poles, zeros and gain to the

components (R1, R2, R3, C1, C2, and C3) in Figure 5. Use

these guidelines for locating the poles and zeros of the

compensation network:

1. Pick gain (R2/R1) for desired converter bandwidth.

2. Place first zero below filter’s double pole (~75% fLC).

3. Place second zero at filter’s double pole.

4. Place first pole at the ESR zero.

5. Place second pole at half the switching frequency.

6. Check gain against error amplifier’s open-loop gain.

7. Estimate phase margin - repeat if necessary.

Compensation Break Frequency Equations

Figure 6 shows an asymptotic plot of the DC/DC converter’s

gain vs frequency. The actual Modulator Gain has a high gain

peak due to the high Q factor of the output filter and is not

shown in Figure 6. Using the previously mentioned guidelines

should give a Compensation Gain similar to the curve plotted.

The open loop error amplifier gain bounds the compensation

gain. Check the compensation gain at fP2 with the capabilities

of the error amplifier. The Closed Loop Gain is constructed on

the graph of Figure 6 by adding the Modulator Gain (in dB) to

the Compensation Gain (in dB). This is equivalent to

multiplying the modulator transfer function to the

compensation transfer function and plotting the gain.

The compensation gain uses external impedance networks

ZFB and ZIN to provide a stable, high bandwidth (BW) overall

loop. A stable control loop has a gain crossing with

-20dB/decade slope and a phase margin greater than

45°. Include worst case component variations when

determining phase margin.

FIGURE 5. VOLTAGE-MODE BUCK CONVERTER

COMPENSATION DESIGN

VOUT

REFERENCE

ESR

VIN

VOSC

ERROR

AMP

PWM

DRIVER

(PARASITIC)

ZFB

REFERENCE

COMP

VOUT

ZFB

ISL6526, ISL6526A

ZIN

COMPARATOR

DRIVER

DETAILED COMPENSATION COMPONENTS

PHASE

VE/A

ZIN

OSC

fLC

 x L

O x CO

------------------------------------------

(EQ. 4)

fESR

 x ESR x C

-------------------------------------------

(EQ. 5)

fZ1

 R



----------------------------------

(EQ. 6)

fZ2

 x R

 x C

-------------------------------------------------------

(EQ. 7)

fP1

 x R

2 x

C1 x C2

C1 C2

----------------------







---------------------------------------------------------

(EQ. 8)

fP2

 x R

3 x C3

------------------------------------

(EQ. 9)

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