ISL6526AEVAL2 datasheet(12/18 Pages) RENESAS

12 / 18 page

ISL6526, ISL6526A

FN9055 Rev 12.00

Page 12 of 18

Sep 30, 2015

Component Selection Guidelines

Charge Pump Capacitor Selection

A capacitor across pins CT1 and CT2 is required to create

the proper bias voltage for the ISL6526, ISL6526A when

operating the IC from 3.3V. Selecting the proper capacitance

value is important so that the bias current draw and the

current required by the MOSFET gates do not overburden

the capacitor. A conservative approach is presented in

Equation 10.

Output Capacitor Selection

An output capacitor is required to filter the output and supply

the load transient current. The filtering requirements are a

function of the switching frequency and the ripple current.

The load transient requirements are a function of the slew

rate (di/dt) and the magnitude of the transient load current.

These requirements are generally met with a mix of

capacitors and careful layout.

Modern digital ICs can produce high transient load slew

rates. High frequency capacitors initially supply the transient

and slow the current load rate seen by the bulk capacitors.

The bulk filter capacitor values are generally determined by

the ESR (Effective Series Resistance) and voltage rating

requirements rather than actual capacitance requirements.

High frequency decoupling capacitors should be placed as

close to the power pins of the load as physically possible. Be

careful not to add inductance in the circuit board wiring that

could cancel the usefulness of these low inductance

components. Consult with the manufacturer of the load on

specific decoupling requirements.

Use only specialized low-ESR capacitors intended for

switching-regulator applications for the bulk capacitors. The

bulk capacitor’s ESR will determine the output ripple voltage

and the initial voltage drop after a high slew-rate transient. An

aluminum electrolytic capacitor’s ESR value is related to the

case size with lower ESR available in larger case sizes.

However, the Equivalent Series Inductance (ESL) of these

capacitors increases with case size and can reduce the

usefulness of the capacitor to high slew-rate transient loading.

Unfortunately, ESL is not a specified parameter. Work with

your capacitor supplier and measure the capacitor’s

impedance with frequency to select a suitable component. In

most cases, multiple electrolytic capacitors of small case size

perform better than a single large case capacitor.

Output Inductor Selection

The output inductor is selected to meet the output voltage

ripple requirements and minimize the converter’s response

time to the load transient. The inductor value determines the

converter’s ripple current and the ripple voltage is a function

of the ripple current. The ripple voltage and current are

approximated by Equations 11 and 12:

Increasing the value of inductance reduces the ripple current

and voltage. However, the large inductance values reduce

the converter’s response time to a load transient.

One of the parameters limiting the converter’s response to

a load transient is the time required to change the inductor

current. Given a sufficiently fast control loop design, the

ISL6526, ISL6526A will provide either 0% or 100% duty

cycle in response to a load transient. The response time is

the time required to slew the inductor current from an initial

current value to the transient current level. During this

interval, the difference between the inductor current and

the transient current level must be supplied by the output

capacitor. Minimizing the response time can minimize the

output capacitance required.

The response time to a transient is different for the

application of load and the removal of load. Equations 13

and 14 give the approximate response time interval for

application and removal of a transient load:

where: ITRAN is the transient load current step, tRISE is the

response time to the application of load, and tFALL is the

response time to the removal of load. The worst case

response time can be either at the application or removal of

load. Be sure to check both of these equations at the

minimum and maximum output levels for the worst case

response time.

FIGURE 6. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN

100

-20

-40

-60

fP1

fZ2

10M

100k

10k

100

OPEN LOOP

ERROR AMP GAIN

fZ1

fP2

fLC

fESR

COMPENSATION

FREQUENCY (Hz)

GAIN

MODULATOR

GAIN

LOOP GAIN

VIN

VOSC

------------------







log

--------





log

CPUMP

IBiasAndGate

VCC fs



------------------------------------ 1.5



(EQ. 10)

I=

VIN - VOUT

fs x L

VOUT

VIN

(EQ. 11)

VOUT = I x ESR

(EQ. 12)

tRISE =

L x ITRAN

VIN - VOUT

(EQ. 13)

tFALL =

L x ITRAN

VOUT

(EQ. 14)

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