AC104Z datasheet(17/66 Pages) BOARDCOM

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Data Sheet

AC104Z

9/9/02

Br oad c om

Document

AC104Z-DS03-405-R

Media Interface

Page 7

In 100Base-FX mode, no filtering is performed. The transmit driver uses a current drive output that is well balanced and

produces a low noise PECL signal. PECL voltage levels are produced with resistive terminations.

In 10Base-T mode, high frequency pre-emphasis is performed to extend the cable-driving distance without the external filter.

The FLP and NLP pulses are also driven out through the 10Base-T driver.

The 10Base-T and 100Base-TX transmit signals are multiplexed to the transmit output driver. This arrangement results in

using the same external transformer for both the 10Base-T and the 100Base-TX. The driver output level is set by a built-in

bandgap reference and an external resistor connected to the IBREF pin. The resistor sets the output current for all modes

of operation. The TXOP/N outputs are open drain devices with a serial source to I/O pad resistance of 10

Ω max.

When the 1:1 transformer is used, the current rating is 40 mA for the 2Vp-p MLT-3 signal, and 100 mA for the 5Vp-p

Manchester signal. You can use a 1.25:1 transmit transformer for a 20 percent reduction in output-driver power, which

decreases the drive current to 32 mA for 100Base-TX operation, and 80 mA for 10Base-T operation.

Adaptive Equalizer

The Phy is designed to accommodate a maximum of 150 meters UTP CAT-5 cable. An AT&T 1061 CAT-5 cable of this

length typically has an attenuation of 31 dB at 100 MHz. A typical attenuation of 100-meter cable is 21 dB. The worst case

100m cable attenuation is around 24-26 dB as defined by TP-PMD specification.

The amplitude and phase distortion from the cable causes inter-symbol interference (ISI) which makes clock and data

recovery difficult. The adaptive equalizer is designed to closely match the inverse transfer function of the twisted-pair cable.

The equalizer can change its equalizer frequency response according to the cable length. The equalizer tunes itself

automatically for any cable, compensating for the amplitude and phase distortion introduced by the cable.

PLL Clock Synthesizer

The Phy includes an on-chip PLL clock synthesizer that generates 50 MHz and 125 MHz clocks for the 100Base-TX circuitry.

The PLL clock generator uses a fully differential VCO cell that introduces very low jitter. The Zero Dead Zone Phase

Detection method implemented in the Phy design provides excellent phase tracking. A charge pump with charge sharing

compensation is also included to further reduce jitter at different loop filter voltages. The on-chip loop filter eliminates the

need for external components and minimizes the external noise sensitivity. Only one external 50 MHz (RMII) or 125 MHz

(SMII) crystal or clock source is required as a reference clock.

After power-on or reset, the PLL clock synthesizer generates the 20 MHz clock output until the 100Base-X operation mode

is selected.

Jabber and SQE (Heartbeat)

After the MAC transmitter exceeds the jabber timer (46mS), the transmit and loopback functions are disabled and the COL

signal is asserted. After TX_EN goes low for more than 500 ms, the TP transmitter reactivates and COL gets de-asserted.

Setting Jabber Disable disables the jabber function.

When the SQE test is enabled, a COL pulse with 5-15BT is asserted after each transmitted packet. SQE is enabled in

10Base-T by default, and can be disabled via SQE Test Inhibit.

Reverse Polarity Detection and Correction

Certain cable plants have crossed wiring on the twisted pairs; the reversal of TXIN and TXIP. Under normal circumstances

this causes the receive circuitry to reject all data. When the Auto Polarity Disable bit is cleared, the Phy detects that either

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