ISL8225MEVAL4Z datasheet(22/34 Pages) RENESAS

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ISL8225M

FN7822 Rev 2.00

Page 22 of 34

December 8, 2014

Application Information

Programming the Output Voltage

The ISL8225M has an internal 0.6V ±0.7% reference voltage.

Programming the output voltage requires a resistor divider (R1

and R2) between the VOUT, VSEN+, and VSEN- pins, as shown in

Figure 18. Please note that the output voltage accuracy is also

dependent on the resistor accuracy of R1 and R2. The user needs

to select a high accuracy resistor (i.e. 0.5%) in order to achieve

the overall output accuracy. The output voltage can be calculated

as shown in Equation 1:

NOTE: It is recommended to use a 1kΩ value for the top resistor, R1. The

value of the bottom resistor for different output voltages is shown in

Table 4.

Due to the minimum off-time limit of 410ns, the module has a

maximum output voltage, depending on input voltage. Refer to

Figure 27 for the 5V input voltage limitation.

At higher output voltage, the inductor ripple increases, which makes

both output ripple and inductor power loss higher. Therefore, higher

switching frequency can be used to reduce the inductor ripple.

However, higher switching frequency results in higher switching loss

and higher gate driving loss, so the overall efficiency may suffer.

Because of thermal and efficiency concerns, the optimal switching

frequency is 750KHz for 6.5V and 7.5V output. With 750kHz

switching frequency, the minimum input voltage is 10V for 6.5V

output and 11V for 7.5V. Please refer to Figure 27 for frequency

selection at different operating conditions, then refer to Figure 31 to

choose RSYNC.

Selection of Input Capacitor

Selection of the input filter capacitor is based on how much

ripple the supply can tolerate on the DC input line. The larger the

capacitor, the less ripple expected, however, consideration

should be given to the higher surge current during power-up. The

ISL8225M provides a soft-start function that controls and limits

the current surge. The value of the input capacitor can be

calculated as shown in Equation 2:

where:

•CIN(MIN) is the minimum required input capacitance (µF)

•IO is the output current (A)

• D is the duty cycle

•VP-P is the allowable peak-to-peak voltage (V)

•fSW is the switching frequency (Hz)

In addition to the bulk capacitance, some low Equivalent Series

Resistance (ESR) ceramic capacitance is recommended to

decouple between the VIN and PGND of each channel. Table 2

shows for some recommended capacitors. This capacitance

reduces voltage ringing created by the switching current across

parasitic circuit elements. All these ceramic capacitors should be

placed as closely as possible to the module pins. The estimated

RMS current should be considered in choosing ceramic capacitors.

Each 10µF X5R or X7R ceramic capacitor is typically good for 2A

to 3A of RMS ripple current. Refer to the capacitor vendor to

check the RMS current ratings. In a typical 15A output

application for one channel, if the duty cycle is 0.5, it needs at

least three 10µF X5R or X7R ceramic input capacitors.

TABLE 4. VALUE OF BOTTOM RESISTOR FOR DIFFERENT OUTPUT

VOLTAGES (VOUT vs R2)

(Ω)

VOUT

(V)

(Ω)

0.6

Open

0.8

3.01k

1.0

1.50k

1.2

1.00k

1.5

665

1.8

491

2.0

422

2.5

316

3.3

221

5.0

137

6.0

110

6.5

102

7.5

86.6

FIGURE 27. RECOMMENDED FREQUENCY vs VIN AT VOUT

VOUT

0.6

--------







(EQ. 1)

500

600

700

800

900

1000

1100

VOUT (V)

12VIN

8VIN

10VIN

15VIN

20VIN

5VIN

CIN MIN



IO D1 D

–





VP-P fSW



-----------------------------------

(EQ. 2)

IIN RMS



Io D 1 D

–





---------------------------------

(EQ. 3)

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