ISL8225MEVAL4Z datasheet(24/34 Pages) RENESAS

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ISL8225M

FN7822 Rev 2.00

Page 24 of 34

December 8, 2014

Soft-Start

The ISL8225M has an internal, digital, precharged soft-start

circuitry (Figures 29 to 31). The circuitry has a rise time inversely

proportional to the switching frequency. Rise time is determined

by a digital counter that increments with every pulse of the phase

clock. The full soft-start time from 0V to 0.6V can be estimated

as shown in Equation 6. The typical soft-start time is ~2.5ms.

The ISL8225M is able to work under a precharged output. The

PWM outputs do not feed to the drivers until the first PWM pulse

is seen. The low-side MOSFET is on for the first clock cycle, to

provide charge for the bootstrap capacitor. If the precharged

output voltage is greater than the final target level but less than

the 113% set point, switching does not start until the output

voltage is reduced to the target voltage and the first PWM pulse

is generated. The maximum allowable precharged level is 113%.

If the precharged level is above 113% but below 120%, the

output hiccups between 113% (LGATE turns on) and 87% (LGATE

turns off), while EN is pulled low. If the precharged load voltage is

above 120% of the targeted output voltage, then the controller is

latched off and cannot power up.

Power-Good

Power-good comparators monitor voltage on the VMON pin. Trip

points are shown in Figure 32. PGOOD is not asserted until the

soft-start cycle is complete. PGOOD pulls low upon both ENs

disabling it or when the VMON voltage is out of the threshold

window. PGOOD does not pull low until the fault presents for

three consecutive clock cycles.

UV indication is not enabled until the end of soft-start. In a UV

event, if the output drops below -13% of the target level due to a

reason other than OV, OC, OT, or PLL faults (cases when EN is not

pulled low), PGOOD is pulled low.

FIGURE 28. SIMPLIFIED ENABLE AND VOLTAGE FEED-FORWARD CIRCUIT

0.8V

IEN_HYS = 30µA

RUP

RDOWN

SOFT-START

RDOWN

RUP V

EN_REF

VEN_FTH VEN_REF

–

---------------------------------------------------------------

VEN_FTH VEN_RTH VEN_HYS

–

VIN

OV, OT, OC, AND PLL LOCKING FAULTS

RUP

VEN_HYS

IEN_HYS

-----------------------------

ON/OFF

384

CYCLES

CLOCK

tSS

1280

fSW

-------------

(EQ. 6)

VOUT TARGET VOLTAGE

0.0V

tSS

1280

fSW

-------------

FIRST PWM PULSE

-100mV

tSS_DLY

384

fSW

------------

FIGURE 29. SOFT-START WITH VOUT = 0V

SS SETTLING AT VREF + 100mV

INIT. VOUT

VOUT TARGET VOLTAGE

FIRST PWM PULSE

-100mV

SS SETTLING AT VREF + 100mV

FIGURE 30. SOFT-START WITH VOUT < TARGET VOLTAGE

OV = 113%

VOUT TARGET VOLTAGE

FIRST PWM PULSE

FIGURE 31. SOFT-START WITH VOUT BELOW 113% BUT ABOVE FINAL

TARGET VOLTAGE

FIGURE 32. POWER-GOOD THRESHOLD WINDOW

-13%

-9%

VREF

+9%

+13%

VMON1, 2

CHANNEL 2 UV/OV

END OF SS1

AND

PGOOD

CHANNEL 1 UV/OV

END OF SS2

+20%

PGOOD

PGOOD LATCH OFF

SS1_PERIOD

AND

SS2_PERIOD

AFTER 120% OV

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