MP6531A – 5V - 60V, THREE-PHASE BLDC MOTOR PRE-DRIVER

MP6531A Rev. 1.02

www.MonolithicPower.com

11

6/20/2017

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© 2017 MPS. All Rights Reserved.

OPERATION

The MP6531A is a three-phase BLDC motor

pre-driver that drives three external N-channel

MOSFET half-bridges with an 0.8A source and

1A of sink current capability. The MP6531A

operates over a wide input voltage range of 5V

to 60V, generating a boosted gate drive voltage

when the input supply is below 12V. The

MP6531A features low-power sleep mode,

which disables the device and draws a very low

supply current. The MP6531A provides several

flexible functions, such as adjustable dead-time

control and over-current protection, which allow

the device to cover a wide range of applications.

Power-Up Sequence

The power-up sequence is initiated by the

application of voltage to VIN. To initiate power-

up, VIN must be above the under-voltage

After power-up begins, the VREG supply begins

before the device becomes functional.

The power-up process takes between 1ms and

2ms, after which the MP6531A responds to the

logic inputs and drives the outputs.

Gate Drive Power Supplies

Gate drive voltages are generated from the

input power (VIN). A regulated charge pump

voltage doubler circuit supplies a voltage of

approximately 11.5V to VREG. This voltage is

used for the low-side gate drive supply. The

charge

pump

requires

external

capacitors

between CPA and CPB and from VREG to

ground.

The high-side gate drive is generated by a

combination of a bootstrap capacitor and an

internal

trickle

charge

pump.

Bootstrap

capacitors are charged to VREG when the low-

side MOSFET (LS-FET) is turned on. This

charge is then used to drive the high-side

MOSFET (HS-FET) gate when it is turned on.

To keep the bootstrap capacitors charged and

allow for operation at 100% duty cycle, an

internal trickle charge pump supplies a small

current (about 5µA) to overcome leakages that

would discharge the bootstrap capacitors.

Sleep Mode (nSLEEP Input)

Driving nSLEEP low puts the device into a low-

power sleep state. In this state, all internal

circuits are disabled, and all inputs are ignored.

nSLEEP has an internal pull-down resistor, so

the pin must be driven high for the MP6531A to

operate.

When

exiting

sleep

mode,

the

MP6531A initiates the power-up sequence.

Input Logic

HC, HB, or HA are used to control the gate

drive for the HS-FET of each phase. LC, LB, or

LA are used to control the gate drive for the

low-side FET. Positive dead time is enforced by

the device, and if both HX and LX are driven

high, neither FET is driven (see Table 1).

Table 1: Input Logic Truth Table

LX

HX

SHX

H

H

High impedance

H

L

GND

L

H

VIN

L

L

High impedance

nFAULT

The nFAULT output reports to the system when

a fault condition (such as output short-circuit,

over-current, or over-temperature) is detected.

nFAULT is an open-drain output and is driven

low when a fault condition occurs. If the fault

condition is released, nFAULT is pulled high by

an external pull-up resistor.

To protect the power stage from damage

implemented in the MP6531A. The voltage drop

across each MOSFET is sensed. This voltage

voltage exceeds the voltage supplied to the

OC_REF terminal, a short circuit is recognized.

In the event of a short circuit, the MP6531A

disables all of the gate drive outputs. nFAULT is

driven active low. The device remains latched

off until it is reset by nSLEEP or VIN UVLO.

Short circuit protection can be disabled by

connection a 100k

Ω resistor from VREG to the

OCREF pin.