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S29CD032G Datasheet(PDF) 75 Page - SPANSION

Part # S29CD032G
Description  CMOS 2.5 VOLT ONLY BURST MODE DUAL BOOT, SIMULTANEOUS READ /WRITE FLASH MEMORY
PDF  93 Pages
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Manufacturer  SPANSION [SPANSION]
Direct Link  http://www.spansion.com
Logo SPANSION - SPANSION

S29CD032G Datasheet(HTML) 75 Page - SPANSION

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March 22, 2004 30606B0
S29CD032G
75
Ad va nc e
In forma t i o n
AC Characteristics
Burst Mode Read
Parameter
Description
Speed Options
Unit
JEDEC
Std.
0R
0P
0M
0J
tBACC Burst Access Time Valid Clock to Output Delay
Max 7.5 FBGA
9 FBGA
9.5 PQFP
10 FBGA
10 PQFP
17
ns
tADVCS ADV# Setup Time to Rising Edge of CLK
Min
6
7
8
9
ns
tADVCH ADV# Hold Time from Rising Edge of CLK
Min
1.5
ns
tADVP ADV# Pulse Width
Min
7.5
8.5
9.5
10.5
ns
tDVCH Valid Data Hold from CLK
Min
2
2
3
3
ns
tDIND CLK to Valid IND/WAIT#
Max 7.5 FBGA
9 FBGA
9.5 PQFP
10 FBGA
10 PQFP
17
ns
tINDH IND/WAIT# Hold from CLK
Min
2
2
3
3
ns
tIACC CLK to Valid Data Out, Initial Burst Access
Max
48
54
64
67
ns
tCLK CLK Period
Min
13.3
15.15
18.85
25
ns
Max
60
tCR CLK Rise Time
Max
3
ns
tCF
CLK Fall Time
Max
3
ns
tCH CLK High Time
Min
2
2.5
2.5
3
ns
tCL
CLK Low Time
Min
2
2.5
2.5
3
ns
tDS Data Setup to WE# Rising Edge
Min
15
16
17
18
ns
tDH Data Hold from WE# Rising Edge
Min
2
ns
tAS
Address Setup to Falling Edge of WE#
Min
5
ns
tAH Address Hold from Falling Edge of WE#
Min
25
26
27
28
ns
tCS
CE# Setup Time
Min
8
ns
tCH CE# Hold Time
Min
8
ns
tACS Address Setup Time to CLK
Min
6
7
8
9
ns
tACH
Address Hold Time from ADV# Rising Edge of CLK
while ADV# is Low
Min
3
ns
tOE Output Enable to Output Valid
Max
20
28
ns
tDF
tOEZ Output Enable to Output High Z
Min
2
2
3
3
ns
Max
7.5
10
15
17
tEHQZ
tCEZ Chip Enable to Output High Z
Max
7.5
10
15
17
ns
tCES CE# Setup Time to Clock
Min
8
9
10
11
ns



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