S29CD032G datasheet(17/93 Pages) SPANSION

17 / 93 page

March 22, 2004 30606B0

S29CD032G

Ad va nc e

In forma t i o n

“Command Definitions” section has details on erasing a sector or the entire chip,

or suspending/resuming the erase operation.

After the system writes the autoselect command sequence, the device enters the

autoselect mode. The system can then read autoselect codes from the internal

cycle timing applies in this mode. Refer to the “Autoselect Mode” section for more

information.

ICC2 and ICC3 in the DC Characteristics table represents the active current speci-

fication for erase or program modes. The AC Characteristics section contains

timing specification tables and timing diagrams for erase or program operations.

When in Synchronous read mode configuration, the device is able to perform both

asynchronous and synchronous write operations. CLK and ADV# address latch is

supported in synchronous programming mode. During a synchronous write oper-

ation, to write a command or command sequence, (which includes programming

data to the device and erasing sectors of memory), the system must drive ADV#

and CE# to VIL, and OE# to VIH when providing an address to the device, and

drive WE# and CE# to VIL, and CE# to VIH, when writing commands or data.

Accelerated Program and Erase Operations

The device offers accelerated program/erase operations through the ACC pin.

When the system asserts VHH (12V) on the ACC pin, the device automatically en-

ters the Unlock Bypass mode. The system may then write the two-cycle Unlock

Bypass program command sequence to do accelerated programming. The device

uses the higher voltage on the ACC pin to accelerate the operation. A sector that

is being protected with the WP# pin will still be protect during accelerated pro-

gram or Erase. Note that the ACC pin must not be at VHH during any operation

other than accelerated programming, or device damage may result.

Autoselect Functions

If the system writes the autoselect command sequence, the device enters the au-

toselect mode. The system can then read autoselect codes from the internal

cycle timings apply in this mode. Refer to the Autoselect Mode and Autoselect

Command Sequence sections for more information.

Automatic Sleep Mode (ASM)

The automatic sleep mode minimizes Flash device energy consumption. While in

asynchronous mode, the device automatically enables this mode when addresses

remain stable for tACC + 60 ns. The automatic sleep mode is independent of the

CE#, WE# and OE# control signals. Standard address access timings provide

new data when addresses are changed. While in sleep mode, output data is

latched and always available to the system. While in synchronous mode, the de-

vice automatically enables this mode when either the first active CLK level is

greater than tACC or the CLK runs slower than 5 MHz. Note that a new burst op-

eration is required to provide new data.

ICC8 in the “DC Characteristics” section represents the automatic sleep mode cur-

rent specification.

Standby Mode

When the system is not responding or writing to the device, it can place the de-

vice in the standby mode. In this mode, current consumption is greatly reduced,

S29CD032G Datasheet(PDF) 17 Page - SPANSION

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