AD9022 datasheet(3/12 Pages) AD

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–3–

ORDERING GUIDE

Temperature

Package

Model

Range

Description

Option

AD9022AQ/BQ –25

°C to +85°C 28-Lead Ceramic DIP Q-28

AD9022AZ/BZ –25

°C to +85°C 28-Pin Ceramic

Z-28

Leaded Chip Carrier

AD9022SQ

–55

°C to +125°C 28-Lead Ceramic DIP Q-28

AD9022SZ

–55

°C to +125°C 28-Pin Ceramic

Z-28

Leaded Chip Carrier

N – 2

N – 1

DATA

OUTPUT

N – 3

N + 1

ANALOG

tOD = 15–27.5 TYPICAL

N + 2

tOD

ENCODE

ta = 0.7 TYPICAL

AD9022 Timing Diagram

ABSOLUTE MAXIMUM RATINGS

+VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V

–VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–6 V

Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . –1.5 V to +1.5 V

Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +VS to 0 V

Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

Operating Temperature Range

AD9022AQ/AZ/BQ/BZ . . . . . . . . . . . . . . . –25

°C to +85°C

AD9022SQ/SZ . . . . . . . . . . . . . . . . . . . . . –55

°C to +125°C

Maximum Junction Temperature

2 . . . . . . . . . . . . . . . . +175

°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300

°C

Storage Temperature Range . . . . . . . . . . . . –65

°C to +150°C

NOTES

1Absolute maximum ratings are limiting values to be applied individually, and

beyond which the serviceability of the circuit may be impaired. Functional

operability is not necessarily implied. Exposure to absolute maximum rating

conditions for an extended period of time may affect device reliability.

2Typical thermal impedances: “Q” Package (Ceramic DIP):

JC = 10

°C/W; θ

JA =

°C/W. “Z” Package (Gullwing Surface Mount): θ

JC = 13

°C/W; θ

JA = 45

°C/W.

AD9022

Test

AD9022AQ/AZ

AD9022BQ/BZ

AD9022SQ/SZ

Parameter (Conditions)

Temp

Level

Min Typ

Max

Min Typ

Max

Min Typ

Max

Units

Two-Tone Intermodulation

Distortion Rejection

+25

°C

dBc

DIGITAL OUTPUTS

Logic Compatibility

TTL

Logic “1” Voltage

Full

2.4

Logic “0” Voltage

Full

0.5

Output Coding

Offset Binary

POWER SUPPLY

+VS Supply Voltage

Full

4.75 5.0

5.25

4.75 5.0

5.25

4.75 5.0

5.25

+VS Supply Current

Full

100

120

100

120

100

120

–VS Supply Voltage

Full

–5.45 –5.2 –4.95

–VS Supply Current

Full

180

220

180

220

180

220

Power Dissipation

Full

1.4

1.9

1.4

1.9

1.4

1.9

Power Supply

Rejection Ratio (PSRR)

Full

mV/V

NOTES

1AD9022 load is a single LS latch.

2RMS signal-to-rms noise with analog input signal 1 dB below full scale at specified frequency. Tested at 55% duty cycle.

3Intermodulation measured with analog input frequencies of 8.9 MHz and 9.8 MHz at 7 dB below full scale.

4PSRR is sensitivity of offset error to power supply variations within the 5% limits shown.

Specifications subject to change without notice.

REV. B

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