MAX86140 datasheet(49/89 Pages) MAXIM

49 / 89 page

The recommended settings for the picket fence algorithm

are the default power on reset values for all registers but

THRESHOLD_SIGMA_MULT bits. Here it is recommended

that the 32x value 0x3 be used so only large excursions

are classified as picket fence events. Lower values of

THRESHOLD_SIGMA_MULT can cause the algorithm to

go off track with extremely noisy waveform.

Photo Diode Biasing

The MAX86140/MAX86141 provides multiple photo diode

biasing options (see Table 15). These options allow the

MAX86140/MAX86141 to operate with a large range of

photo diode capacitance. The PDBIAS values adjust the

PD_IN bias point impedance to ensure that the photo

diode settles rapidly enough to support the sample timing.

As the PDBIAS values goes up, the input-referred noise

of the MAX86140/MAX86141 goes up. The relationship

between PDBIAS and noise with increasing photo diode

capacitance is illustrated in the "Input Referred Noise

vs. PD Capacitance" graph of the Typical Operating

Characteristics section. Because of the increased noise

with PDBIAS, the lowest recommended PDBIAS values

should be used for a given photo diode capacitance.

Layout Guidelines

The MAX86140/MAX86141 is a high dynamic range analog

front-end (AFE) and its performance can be adversely

impacted by the physical printed circuit board (PCB)

layout. Maxim recommends that all bypass recommendations

in the pin table be followed. Specifically, it is

recommended that the VDD_ANA and VDD_DIG pins be

shorted at the PCB. Maxim also recommends that GND_

ANA, GND_DIG, and PGND be shorted to a single PCB

ground plane. These three pins have been assigned along

a single column so they can be shorted and combined into

a single via on the edge of the WLP grid array.

The combined VDD_ANA and VDD_DIG pins should

then be decoupled with a 0.1µF or larger ceramic chip

capacitor to the PCB ground plane. In addition, the VREF

pin should be decoupled to the PCB GND plane with a

1.0μF ceramic capacitor. The voltage on the VREF pin

is nominally 1.21V, so a 6.3V rated ceramic capacitor

should be adequate for this purpose. It is recommended

that all decoupling caps use individual vias to the PCB

GND plane to avoid mutual impedance coupling between

decoupled supplies when sharing vias.

The most critical aspect of the PCB layout of MAX86140/

MAX86141 is the handling of the PD_IN and PD_

GND nodes. Parasitic capacitive coupling to the PD_IN

can result in additional noise being injected into the

MAX86140/MAX86141 front-end. To minimize external

interference coupling to PD_IN, it is recommended that

the PD_IN node be fully shielded by the PD_GND node.

An example of this recommendation is shown below.

In the three layers shown, the PD_IN node is shielded

with a coplanar PD_GND trace on the top layer, the

layer on which the MAX86140/MAX86141 is mounted.

On the bottom layer, the photo diode cathode is entirely

shielded with the PD_GND shield, which is also the photo

diode anode. Note, also, that the PD_GND shield also is

extended below the photo diode. This is done because,

in most photo diodes, the cathode is the bulk of the

silicon. Therefore, shielding beneath the photo diode will

terminate the capacitance to the bulk or cathode side to

the reference node (PD_GND). On the layer just above

the bottom (layer 5, in this case), the section of the GND

plane has been opened up, connected to PD_GND to

shield the PD_IN node below the photo diode cathode

contact. Finally, the PD_GND pin should only be attached

to the PCB GND in only one point. This is shown on the

top layer.

Table 15. Recommended PDBIAS Values Based on the Photo Diode Capacitance

PDBIAS<2:0>

PHOTO DIODE CAPACITANCE

0x001

0pF to 65pF

0x101

65pF to 130pF

0x110

130pF to 260pF

0x111

260pF to 520pF

All other values

Not recommended

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