MAX86140 datasheet(53/89 Pages) MAXIM

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SPI Timing

Detailed SPI Timing

The detailed SPI timing is illustrated below. The timings

indicated are all specified in the Electrical Characteristics

table.

Single-Word SPI Register Read/Write Transaction

The MAX86140/MAX86141 is SPI/QSPI/Micro-wire/DSP

compatible. The operation of the SPI interface is shown

below. Data is strobed into the MAX86140/MAX86141 on

the SCLK rising edge while clocked out on the SCLK falling

edge. All single-word SPI read and write operations are

done in a 3-byte, 24 clock cycle SPI instruction framed by

a CSB low interval. The content of the SPI operation con-

sists of a one-byte register address (A[7:0]), followed by a

one-byte command word that defines the transaction as

write or read, followed by a single-byte data word either

written to, or read from, the register location provided in

the first byte.

Write mode operations will be executed on the 24th SCLK

rising edge using the first three bytes of data available. In

write mode, any data supplied after the 24th SCLK

rising edge will be ignored. Subsequent writes require

CSB to deassert high and then assert low for the next write

command. A rising CSB edge preceding the 24th rising

edge of SCLK by tCSA (detailed SPI timing diagram), will

result in the transaction being aborted.

Figure 36. Detailed SPI Timing Diagram

Figure 37. SPI Write Transaction

A7 A6 A5 A4 A3 A2 A1 A0

DIN2 DIN1 DIN0

R/W

A7'

DO2 DO2 DO0

tDS

tDH

tCH

tCL

tCP

tCSS0

tCSH0

tDOE

tCSPW

tDOT

tCSH1

tCSF

tDOZ

tPLGPIOx

SDI

SCLK

CSB

SDO

GPIOx

DON’T CARE

Command Executed

Ignored

Edges

CSB

SDI

SCLK

SDO

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