Philips Semiconductors

Product data sheet

PCA9541

2004 Oct 01

7

Register 0: Interrupt Enable (IE) Register (B1B0 = 00)

This register allows a master to read and/or write (if needed) Mask options for its own channel.

The Interrupt Enable Register described below is identical for both the masters. Nevertheless, there are physically 2 internal Interrupt Enable

Registers, one for each upstream channel.

When Master 0 reads/writes in this register, the internal Interrupt Enable Register 0 will be accessed.

When Master 1 reads/writes in this register, the internal Interrupt Enable Register 1 will be accessed.

BIT

7

6

5

4

3

2

1

0

SYMBOL

0

0

0

0

BUSLOSTMSK

BUSOKMSK

BUSINITMSK

INTINMSK

Table 2.

Register 0

BIT

SYMBOL

READ/

WRITE

DEFAULT

DESCRIPTION

0

INTINMSK

R/W

0

0: Interrupt on INT_IN will generate an interrupt on INT

0

INTINMSK

R/W

0

1: Interrupt on INT_IN will not generate an interrupt on INT (masked)

1

BUSINITMSK

R/W

0

0: After connection is requested and Bus Initialization requested (BUSINIT = 1), an

interrupt on INT will be generated when the bus initialization is done.

Note: Channel switching is done after bus initialization completed.

1

BUSINITMSK

R/W

0

1: After connection is requested and Bus Initialization requested (BUSINIT = 1), an

interrupt on INT will not be generated when the bus initialization is done (masked).

Note: Channel switching is done after bus initialization completed.

2

BUSOKMSK

R/W

0

0: After connection is requested and Bus Initialization not requested (BUSINIT = 0), an

interrupt on INT will be generated when a non-Idle situation has been detected on the

downstream slave channel by the bus sensor at the switching moment.

Note: Channel switching is done automatically after the STOP command.

2

BUSOKMSK

R/W

0

1: After connection is requested and Bus Initialization not requested (BUSINIT = 0), an

interrupt on INT will not be generated when a non-Idle situation has been detected on

the downstream slave channel by the bus sensor at the switching moment (masked).

Note: Channel switching is done automatically after the STOP command.

3

BUSLOSTMSK

R/W

0

0: An interrupt on INT will be generated after the other master has been been

disconnected

3

BUSLOSTMSK

R/W

0

1: An interrupt on INT will not be generated after the other master has been been

disconnected.

4

NOT USED

R only

0

5

NOT USED

R only

0

6

NOT USED

R only

0

7

NOT USED

R only

0

NOTE:

Default values are the same for PCA9541/01, PCA9541/02, and PCA9541/03