Philips Semiconductors

Product data sheet

PCA9541

2004 Oct 01

22

AC CHARACTERISTICS

SYMBOL

PARAMETER

STANDARD-MODE

FAST-MODE

UNIT

MIN

MAX

MIN

MAX

—

—

ns

SCL clock frequency

0

100

0

400

kHz

SCL bus initialization/recovery clock frequency

50

150

50

150

kHz

Bus free time between a STOP and START condition

4.7

—

1.3

—

µs

Hold time (repeated) START condition

After this period, the first clock pulse is generated

4.0

—

0.6

—

µs

LOW period of the SCL clock

4.7

—

1.3

—

µs

HIGH period of the SCL clock

4.0

—

0.6

—

µs

Set-up time for a repeated START condition

4.7

—

0.6

—

µs

Set-up time for STOP condition

4.0

—

0.6

—

µs

Data hold time

3.45

0.9

µs

Data set-up time

250

—

100

—

ns

Rise time of both SDA and SCL signals

—

1000

300

ns

Fall time of both SDA and SCL signals

—

300

300

µs

Capacitive load for each bus line

—

400

—

400

µs

Pulse width of spikes which must be suppressed

by the input filter

—

50

—

50

ns

—

1

—

1

µs

—

0.6

—

0.6

µs

Data valid Acknowledge

—

1

—

1

µs

INT0 and INT1 outputs

INT_in to INT1 or INT2 active valid time

—

4

—

4

µs

INT_in to IINT1 or INT2 inactive delay time

—

2

—

2

µs

LOW level pulse width rejection or INT_in input

1

—

1

—

ns

HIGH level pulse width rejection or INT_in input

0.5

—

0.5

—

µs

RESET

Pulse width LOW reset

4

—

4

—

ns

Reset time (SDA clear)

500

—

500

—

ns

0

—

0

—

ns

NOTES:

1. Pass gate propagation delay is calculated from the 20

the undefined region of the falling edge of SCL.

4. Measurements taken with 1 k

Ω pull-up resistor and 50 pF load.

5. Resetting the device while actively communicating on the bus may cause glitches or errant STOP conditions.