Philips Semiconductors

Product data sheet

PCA9541

2004 Oct 01

12

Register 2: Interrupt Status Register (B1B0 = 10)

The Interrupt Status Register for both the masters is identical and is described below. Nevertheless, there are physically 2 internal Interrupt

Registers, one for each upstream channel.

When Master 0 reads this register, the internal Interrupt Register 0 will be accessed.

When Master 1 reads this register, the internal Interrupt Register 1 will be accessed.

BIT

7

6

5

4

3

2

1

0

SYMBOL

NMYTEST

MYTEST

0

0

BUSLOST

BUSOK

BUSINIT

INTIN

Table 8.

Register 2

BIT

SYMBOL

READ/

WRITE

DEFAULT

DESCRIPTION

0

INTIN

R only

0

0: No interrupt on interrupt input (INT_IN)

0

INTIN

R only

0

1: Interrupt on interrupt input (INT_IN)

0: No interrupt generated by the bus recovery/initialization function

1

BUSINIT

R only

0

1: Interrupt generated by the bus recovery/initialization function –

recovery/initialization done

0: No interrupt generated by bus sensor function

2

BUSOK

R only

0

1: Interrupt generated by bus sensor function (masked when bus

recovery/initialization requested) – Bus was not idle when the switch

occurred

3

BUSLOST

R only

0

0: No interrupt generated to the previous master when switching to the new

one is initiated

3

BUSLOST

R only

0

1: Interrupt generated to the previous master when switching to the new

one is initiated

4

NOT USED

R only

0

5

NOT USED

R only

0

6

MYTEST

R only

0

0: No interrupt generated by TESTON bit f (TESTON = 0)

6

MYTEST

R only

0

1: Interrupt generated by TESTON bit (TESTON = 1)

7

NMYTEST

R only

0

0: No interrupt generated due to NTESTON bit from the other master

(NTESTON = 0 from the other master)

7

NMYTEST

R only

0

1: Interrupt generated due to TESTON bit from the other master

(NTESTON = 1 from the other master)

NOTES:

1. Interrupt on a master is cleared after TESTON bit is cleared the same master or NTESTON bit is cleared by the other master.

2. If the interrupt condition remains on INT_IN after the Read sequence, another interrupt will be generated (if the interrupt has not been

masked)

3. Default values are the same for PCA9541/01, PCA9541/02 and PCA9541/03

4. Reading the Interrupt Status Register does not clear the MYTEST, NMYTEST or the INTIN bits. They are cleared if:

– INT_IN lines goes HIGH for INTIN bit

– TESTON bit is cleared for MYTEST bit

– NTESTON bit is cleared for NMYTEST bit

5. BUSINIT, BUSOK and BUSLOST bits in the Interrupt Status Register gets cleared after a Read of the same register is done. Precisely, the

register gets cleared on the second clock pulse during the read operation.