ZL2008 datasheet(36/43 Pages) RENESAS

36 / 43 page

ZL2008

FN6859 Rev 4.00

Page 36 of 43

April 29, 2011

dropped or faults then the device with the next lowest position

number will become the new reference device.

SMBus Address (SA0, SA1 Pins)

Assign sequential SMBus addresses to each device in the current

sharing group. If other non-current sharing devices are connected

to the same SMBus then assign addresses to these devices that

are before or after the current sharing group.

Current Share Pin-Straps (CFG0, CFG2 Pins)

Resistor pin-strap the CFG0 pin to set the following parameters:

a. Current Share # of Members – Number of devices or phases

in a current sharing group (2 minimum and 8 maximum).

b. Current Share Control – Current sharing is automatically

enabled when the number of members is 2 (and disabled

when members is = 0).

Resistor pin-strap the CFG2 pin to set the current share position:

c. Current Share Position – Sequential numbering from 0 to 7

(max) of N number of members starting with the reference

device in position 0 and ending with the last member device

in position N-1.

For the 3-phase group the parameters for each device are shown

in Table 32.

SYNC Clock (CFG1 Pin)

Typically the reference device sources the SYNC clock. However,

any device internal or external to the current sharing group can

source the SYNC clock. If the reference device is sourcing the

SYNC clock, then resistor pin-strap the CFG1 pin to configure the

SYNC pin as an output. Otherwise configure the reference

device’s SYNC pin as an input. For member devices, resistor

pin-strap the CFG1 pin to configure the SYNC pin as an input.

Soft-start (SS Pin)

Current sharing groups require proper synchronization prior to

ramp events. Resistor pin-strap the SS pin to set the following

parameters:

a. Delay Time – The reference device’s soft-start delay time

must be at least 10ms greater than any member device to

ramp up/down current sharing. The reference device requires

this additional time to coordinate a synchronization signal to

all member devices.

b. Ramp Time – A minimum soft-start ramp time of 5ms is

required for both reference and member devices to ramp

up/down current sharing.

Phase Enable (PH_EN Pin)

Phase enable is used to dynamically add or drop a current

sharing phase during operation. Set the PH_EN pin high to

enable a phase and low to disable a phase (open is an invalid

state). The PH_EN pin replaces the PHASE_CONTROL command.

For proper operation, the pin must be externally driven high or

low without switching glitches. Also, ensure phase enable is high

for the reference and member devices of a current sharing group

prior to ramp-up.

MFR_CONFIG Command

Application specific values are set by the MFR_CONFIG

command. The following parameters must be set to properly

configure current sharing.

a. Current Sense Blanking Delay (bits 15:11) – The current

sense delay parameter controls the blanking time when no

current measurement is taken. This allows the filtering of

noise from the current measurement circuit when the FETs

are switching. The actual value selected depends on fSW,

sensing method and ring-out duration. The same delay is

used for both reference and member devices.

b. Current Sense Control (bits 5:4) – Three modes of current

sensing are available depending on duty cycle and switching

frequency as listed in Table 33 (also refer to “Current Limit

Threshold Selection” on page 21). The same sensing is used

for both reference and member devices.

TABLE 32. Current Share Parameters

Device

SMBus Address

# of Members

Position

Control

Reference

0x20

Enabled

Member_1

0x21

Enabled

Member_2

0x22

Enabled

Rail_1

Rail DDC ID = 5

DEV_2

0x21

Rout Cout

SCL

DDC

PH_3

PH_2

PH_1

3.3V

VCC

DEV_3

0x22

SYNC_Out

VCC

SDA

MEM_1

POS_2

REF.

POS_1

MEM_2

POS_3

DEV_1

0x20

SYNC_In

SYNC

SYNC_In

POS_0

POS_1

POS_2

Rail_1

Rail DDC ID = 5

DEV_2

0x21

Rout Cout

SCL

DDC

PH_3

PH_2

PH_1

3.3V

VCC

DEV_3

0x22

SYNC_Out

VCC

SDA

MEM_1

POS_2

REF.

POS_1

MEM_2

POS_3

DEV_1

0x20

SYNC_In

SYNC

SYNC_In

POS_0

POS_1

POS_2

FIGURE 24. 3-phase Current Sharing Group

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