PC87322VF datasheet(55/84 Pages) NSC

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60 Serial Ports (Continued)

TABLE 6-5 PC87322VF Interrupt Control Functions

FIFO Mode

Interrupt Identification

Interrupt Set and Reset Functions

Only

Bit 3

Bit 2

Bit 1

Bit 0

Priority

Interrupt Type

Interrupt Source

Interrupt Reset Control

Level

None

Highest Receiver Line Status

Overrun Error Parity Error

Reading the Line

Framing Error or Break

Status Register

Interrupt

Second Received Data Available Receiver Data Available

Read Receiver Buffer

Second Character

No Characters have been

Reading the Receiver

Time-Out

removed from or input to the

Buffer Register

Indication

RCVR FIFO during the last 4

char times and there is at least

1 char in it during this time

Third

Transmitter Holding

Reading the IIR Register

(if Source of Interrupt) or

Writing the Transmitter

Holding Register

Fourth MODEM Status

Clear to Send or Data Set

Reading the MODEM

Ready or Ring Indicator

Status Register

or Data Carrier Detect

Bit 3

This bit enables the interrupt when set No exter-

nal pin is associated with this bit other than

IRQ34 In Local Loopback Mode this bit controls

bit 7 of the MODEM Status Register

Bit 4

This bit provides a Local loopback feature for diag-

nostic testing of the UART When bit 4 is set to

logic 1 the following occur the transmitter Serial

Output (SOUT) is set to the Marking (logic 1) state

the receiver Serial Input (SIN) is disconnected the

output of the Transmitter Shift Register is ‘‘looped

back’’ (connected) to the Receiver Shift Register

the four MODEM Control inputs (DSR CTS RI

and DCD) are disconnected and the DTR RTS

OUT1 IRQ ENABLE bits in MCR are internally

connected to DSR CTS RI and DCD in MSR re-

spectively The MODEM Control output pins are

forced to their high (inactive) states In the Loop-

back Mode data that is transmitted is immediately

received This feature allows the processor to veri-

fy the transmit-and-received-data paths of the seri-

al port

In the Loopback Mode the receiver and transmit-

ter interrupts are fully operational The MODEM

Status Interrupts are also operational but the in-

terrupts’ sources are the lower four bits of MCR

instead of the four MODEM control inputs Writing

a 1 to any of these 4 MCR bits will cause an inter-

rupt In Loopback Mode the interrupts are still con-

trolled by the Interrupt Enable Register The IRQ3

and IRQ4 pns will be TRI-STATE in the Loopback

Mode

Bits 5 – 7

These bits are permanently set to logic 0

629 Modem Status Register (MSR)

This register provides the current state of the control lines

from the MODEM (or peripheral device) to the CPU In addi-

tion to this current-state information

four bits of the

MODEM Status Register provide change information These

bits are set to a logic 1 whenever a control input from the

MODEM changes state They are reset to logic 0 whenever

the CPU reads the MODEM Status Register Table 6-2

shows the contents of the MSR Details on each bit follow

Bit 0

This bit is the Delta Clear to Send (DCTS) indicator

Bit 0 indicates that the CTS input to the chip has

changed state since the last time it was read by the

CPU

Bit 1

This bit is the Delta Data Set Ready (DDSR) indica-

tor Bit 1 indicates that the DSR input to the chip has

changed state since the last time it was read by the

CPU

Bit 2

This bit is the Trailing Edge of Ring Indicator (TERI)

detector Bit 2 indicates that the RI input to the chip

has changed from a low to a high state

Bit 3

This bit is the Delta Data Carrier Detect (DDCD) in-

dicator Bit 3 indicates that the DCD input to the

chip has changed state

Note

Whenever bit 0 1 2 or 3 is set to logic 1 a MODEM Status

Interrupt is generated

Bit 4

This bit is the complement of the Clear to Send

(CTS) input If bit 4 (loopback) of the MCR is set to a

1 this bit is equivalent to RTS in the MCR

Bit 5

This bit is the complement of the Data Set Ready

(DSR) input If bit 4 of the MCR is set to a 1 this bit

is equivalent to DTR in the MCR

Bit 6

This bit is the complement of the Ring Indicator (RI)

input If bit 4 of the MCR is set to a 1 this bit is

equivalent to OUT1 in the MCR

Bit 7

This bit is the complement of the Data Carrier De-

tect (DCD) input If bit 4 of the MCR is set to a 1 this

bit is equivalent to IRQ ENABLE in the MCR

6210 Scratchpad Register (SCR)

This 8-bit ReadWrite Register does not control the UART

in any way It is intended as a scratchpad register to be used

by the programmer to hold data temporarily

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