PC87322VF datasheet(11/84 Pages) NSC

11 / 84 page

10 Pin Description (Continued)

Symbol

Function

RDATA

Read Data

This input is the raw serial data read from the floppy disk drive

Read Data

This pin provides an additional Read Data signal in PPM Mode when PNF e 0 (See PD3

and Table 7-5 for further information)

RI12

70 62

Ring Indicator

When low this indicates that a telephone ringing signal has been received by the

MODEM The RI signal is a MODEM status input whose condition the CPU can test by reading bit 6 (RI)

of the MODEM Status Register (MSR) for the appropriate serial channel Bit 6 is the complement of the

RI signal Bit 2 (TERI) of the MSR indicates whether the RI input has changed from low to high since the

previous reading of the MSR

Note

Whenever the TERI bit of the MSR is set an interrupt is generated if MODEM Status interrupts are enabled

RTS12

74 66

Request to Send

When low this output indicates to the MODEM or data set that the UART is ready to

exchange data The RTS signal can be set to an active low by programming bit 1 (RTS) of the MODEM

Control Register to a high level A Master Reset operation sets this signal to its inactive (high) state

Loop mode operation holds this signal to its inactive state (See CFG0 – 4 for further information)

SIN12

75 67

Serial Input

This input receives composite serial data from the communications link (peripheral device

MODEM or data set)

SLCT

Select

This input is set high by the printer when it is selected This pin has a nominal 25 kX pull-down

resistor attached to it

SLIN

Select Input

When this signal is low it selects the printer This pin will be in a TRI-STATE condition

10 ns after a zero is loaded into the corresponding Control Register bit The system should pull this pin

high using a 47 kX resistor (See ASTRB STEP and Table 75 for further information)

SOUT12

73 65

Serial Output

This output sends composite serial data to the communications link (peripheral device

MODEM or data set) The SOUT signal is set to a marking state (logic 1) after a Master Reset

operation (See BOUT and CFG0 – 4 for further information)

STB

Data Strobe

This output indicates to the printer that valid data is available at the printer port This pin

will be in a TRI-STATE condition 10 ns after a zero is loaded into the corresponding Control Register bit

The system should pull this pin high using a 47 kX resistor (See WRITE for further information)

STEP

Step

This output signal issues pulses to the disk drive at a software programmable rate to move the

head during a seek operation

Step

This pin provides an additional step signal in PPM Mode when PNF e 0 (See SLIN ASTRB and

Table 7-5 for further information)

Terminal Count

Control signal from the DMA controller to indicate the termination of a DMA transfer

TC is accepted only when DACK is active TC is active high in PC-AT and Model 30 modes and active

low in PS2 mode

TRK0

Track 0

This input indicates to the controller that the head of the selected floppy disk drive is at track

zero

Track 0

This pin provides an additional Track 0 signal in PPM Mode when PNF e 0 (See PD1 and

Table 7-5 for further information)

VDDA

Analog Supply

This pin is the 5V supply for the analog data separator

VDDBC

50 99

Digital Supply

This is the 5V supply voltage for the digital circuitry

VLD01

56 63

Valid Data

These input pins are sensed during reset and determine the state of bit 5 in the FDC Tape

Drive Register (3F3h) Thus they determine whether bits 6 and 7 of this register contain valid media ID

information for floppy drives 0 and 1 If VLD0 is sensed low at reset then whenever drive 0 is accessed

bit 5 of the Tape Drive Register is a 0 indicating that bits 6 and 7 contain valid media ID information If

VLD0 is sensed high at reset then whenever drive 0 is accessed bit 5 of the Tape Drive Register is a 1

indicating that bits 6 and 7 do not contain valid media ID information The same is true of VLD1 relative

to the media ID information for drive 1 If bit 0 of FCR is 1 the VLD bits have no meaning VLD0 value

during reset is loaded into bit 0 of FCR (to select between media sense or DRATE) A 30 kX internal

pull-down resistor is on each pin Use a 10 kX resistor to pull these pins to high during reset

VSSA

Analog Ground

This is the analog ground for the data separator

VSSB-E

42 9

Digital Ground

This is the ground for the digital circuitry

90 61

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