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PC87322VF Datasheet(PDF) 69 Page - National Semiconductor (TI) |
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PC87322VF Datasheet(HTML) 69 Page - National Semiconductor (TI) |
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69 / 84 page ![]() 90 Device Description (Continued) 926 Receiver Timing Symbol Parameter Conditions Min Max Units tRAI Delay from Active Edge of RD to Reset IRQ 78 ns tRINT Delay from Inactive Edge of RD (RD LSR) to Reset IRQ 55 ns tSCD Delay from RCLK to Sample Time (Note 1) 41 ns tSINT Delay from Stop Bit to Set Interrupt 2 BAUDOUT Cycles Note 1 This is an internal timing and is therefore not tested TLC11870 – 34 FIGURE 9-6a Receiver Timing TLC11870 – 35 Note 2 If SCR0 e 1 then tSINT e 3 RCLKs For a Timeout interrupt tSINT e 8 RCLKs FIGURE 9-6b PC87322VF FIFO Mode Receiver Timing 69 |
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