PC87322VF datasheet(59/84 Pages) NSC

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70 Parallel Port (Continued)

3 If WAIT is low during the host read cycle then the EPP

pulls IOCHRDY low

When WAIT goes high the EPP stops pulling IOCHRDY

to low

4 When IOCHRDY goes high it causes RD to go high If

WAIT is high during the host read cycle then the EPP

does not pull IOCHRDY to low

5 When RD goes high it causes the EPP to pull ASTRB

high

Only when ASTRB is high can the EPP change PD0 – 7

After ASTRB goes high the EPP TRI-STATEs D0 – 7

TLC11870 – 23

FIGURE 7-2 EPP 17 Address Read

EPP 17 Data Write and Data Read

This procedure writes to the selected peripheral device or

An EPP 17 data write operation is similar to the EPP 17

address write operation and an EPP 17 data read opera-

tion is similar to the EPP 17 address read operation except

that the data strobe (DSTRB signal) and a data register

replace the address strobe (ASTRB signal) and the address

EPP Zero Wait State (ZWS) Address Write Operation

(both 17 and 19)

The following procedure performs a short write to the se-

lected peripheral device or register

ZWS should be configured as follows bit 5 of FCR is 1 and

bit 6 of FCR is 0

1 The host writes a byte to the EPP address register WR

goes low to latch D0 – 7 into the data register The latch

drives the data register onto PD0 – 7

2 The EPP first pulls WRITE low and then pulls ASTRB low

to indicate that data has been sent

3 If WAIT is high during the host write cycle ZWS goes low

and IOCHRDY goes high

4 When the host pulls WR high the EPP pulls ASTRB

ZWS and WRITE to high

Only when WRITE and ASTRB are high can the EPP

change PD0 – 7

5 If the peripheral is fast enough to pull WAIT low before

the host terminates the write cycle

the EPP pulls

IOCHRDY to low but does not pull ZWS to low thus

carrying out a normal (non-ZWS EPP 17) write operation

EPP Zero Wait State (ZWS) Data Write Operation (both

17 and 19)

An EPP 17 and 19 Zero Wait State data write operation is

similar to the EPP Zero Wait State address write operation

with the exception that the data strobe (DSTRB signal) and

a data register replace the address strobe (ASTRB) signal

and the address register respectively

TLC11870 – 24

FIGURE 7-3 EPP Write with ZWS

EPP 19 Address Write

The following procedure selects a peripheral or register

1 The host writes a byte to the EPP address register

2 The EPP pulls IOCHRDY low and waits for WAIT to go

low

3 When WAIT goes low the EPP pulls WRITE to low and

drives the latched byte onto PD0 – 7

If WAIT was already low steps 2 and 3 occur concurrent-

4 The EPP pulls ASTRB low and waits for WAIT to go high

5 When WAIT goes high the EPP stops pulling IOCHRDY

low pulls ASTRB high and waits for WAIT to go low

6 Only if no EPP write is pending when WAIT goes low (or

when bit 7 of PTR is 1 and the direction is changed to

Backwards by setting bit 5 of CTR to 1) the EPP pulls

WRITE to high

If an EPP write is pending WRITE remains low and the

EPP may change PD0 – 7

TLC11870 – 25

FIGURE 7-4 EPP 19 Address Write

EPP 19 Address Read

The following procedure reads from the address register

1 The host reads a byte from the EPP address register

When RD goes low the EPP pulls IOCHRDY low and

waits for WAIT to go low

PC87322VF Datasheet(PDF) 59 Page - National Semiconductor (TI)

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