THS10082

SLAS254B – MAY 2002 – REVISED NOVEMBER 2002

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SINGLE CONVERSION MODE

In single conversion mode, a single conversion of the selected analog input channels is performed. The single conversion

mode is selected by setting bit 1 of control register 0 to 1.

A single conversion is initiated by pulsing the CONVST input. On the falling edge of CONVST, the sample and hold stages

of the selected analog inputs are placed into hold simultaneously, and the conversion sequence for the selected channels

is started.

The conversion clock in single conversion mode is generated internally using a clock oscillator circuit. The signal DATA_AV

(data available) becomes active when the trigger level is reached and indicates that the converted sample(s) is (are) written

into the FIFO and can be read out. The trigger level in the single conversion mode can be selected according to Table 13.

Figure 26 shows the timing of the single conversion mode. In this mode, up to two analog input channels can be selected

to be sampled simultaneously (see Table 2).

CONVST

AIN

Sample N

t1

t1

td(A)

t2

tDATA_AV

DATA_AV,

Trigger Level = 1

Figure 26. Timing of Single Conversion Mode

a trigger level which is equivalent to the number of selected analog input channels. For all other trigger level conditions refer

to the timing specifications of single conversion mode.

CONTINUOUS CONVERSION MODE

The internal clock oscillator used in the single-conversion mode is switched off in continuous conversion mode. In

continuous conversion mode, (bit 1 of control register 0 set to 0) the ADC operates with a free running external clock signal

CONV_CLK. With every rising edge of the CONV_CLK signal a new converted value is written into the FIFO.

Figure 27 shows the timing of continuous conversion mode when one analog input channel is selected. The maximum

throughput rate is 8 MSPS in this mode. The timing of the DATA_AV signal is shown here in the case of a trigger level set

to 1 or 4.