THS10082

SLAS254B – MAY 2002 – REVISED NOVEMBER 2002

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READING DATA FROM THE FIFO

The THS10082 informs the connected processor via the digital output DATA_AV (data available) that a block of conversion

values is ready to be read. The block size to be read is always equal to the setting of the trigger level. The selectable trigger

levels depend on the number of selected analog input channels. For example, when choosing one analog input, a trigger

level of 1, 4, 8, and 14 can be selected. The following figures demonstrate the principle of reading the data (the READ signal

is asynchronous to CONV_CLK).

In Figure 30, a trigger level of 1 is selected. The control signal DATA_AV is set to an active low pulse. This means that the

connected processor has the task to read 1 value from the ADC after every DATA_AV low pulse.

CONV_CLK

DATA_AV

READ

Figure 30. Trigger Level 1 Selected

In Figure 31, a trigger level of 4 is selected. The control signal DATA_AV is set to an active low pulse. This means that the

connected processor has the task to read 4 values from the ADC after every DATA_AV low pulse.

CONV_CLK

DATA_AV

READ

Figure 31. Trigger Level 4 Selected

In Figure 32, a trigger level of 8 is selected. The control signal DATA_AV is set to an active low pulse. This means that the

connected processor has the task to read 8 values from the ADC after every DATA_AV low pulse.

CONV_CLK

DATA_AV

READ

Figure 32. Trigger Level 8 Selected

In Figure 33, a trigger level of 14 is selected. The control signal DATA_AV is set to an active low pulse. This means that

the connected processor has the task to read 14 values from the ADC after every DATA_AV low pulse.

CONV_CLK

DATA_AV

READ

Figure 33. Trigger Level 14 Selected

As shown in Figure 30 through Figure 33, READ, is the logical combination of CS0, CS1, and RD.