THS10082

SLAS254B – MAY 2002 – REVISED NOVEMBER 2002

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24

ANALOG INPUT CHANNEL SELECTION

The analog input channels of the THS10082 can be selected via bits 3 to 7 of control register 0. One single channel

(single-ended or differential) is selected via bit 3 of control register 0. Bit 5 controls the selection between single-ended and

differential configuration. Bit 6 selects the autoscan mode, if more than one input channel is selected. Table 10 shows the

possible selections.

Table 10. Analog Input Channel Configurations

BIT 7

SCAN

BIT 6

DIFF1

BIT 5

DIFF0

BIT 4

CHSEL1

BIT 3

CHSEL0

DESCRIPTION OF THE SELECTED INPUTS

0

0

0

0

0

Analog input AINP (single ended)

0

0

0

0

1

Analog input AINM (single ended)

0

0

0

1

0

Reserved

0

0

0

1

1

Reserved

0

0

1

0

0

Differential channel (AINP–AINM)

0

0

1

0

1

Reserved

1

0

0

0

1

Autoscan two single-ended channels: AINP, AINM, AINP,

…

1

0

0

1

0

Reserved

1

0

0

1

1

Reserved

1

0

1

0

1

Reserved

1

0

1

1

0

Reserved

1

1

0

0

1

Reserved

0

0

1

1

0

Reserved

0

0

1

1

1

Reserved

1

0

0

0

0

Reserved

1

0

1

0

0

Reserved

1

0

1

1

1

Reserved

1

1

0

0

0

Reserved

1

1

0

1

0

Reserved

1

1

0

1

1

Reserved

1

1

1

0

0

Reserved

1

1

1

0

1

Reserved

1

1

1

1

0

Reserved

1

1

1

1

1

Reserved

Test Mode

The test mode of the ADC is selected via bit 8 and bit 9 of control register 0. The different selections are shown in Table 11.

Table 11. Test Mode

BIT 9

TEST1

BIT 8

TEST0

OUTPUT RESULT

0

0

Normal mode

0

1

VREFP

1

0

((VREFM)+(VREFP))/2

1

1

VREFM

Three different options can be selected. This feature allows support testing of hardware connections between the ADC and

the processor.