AD805

–5–

REV. 0

POWER

SPLITTER

+

+

+

–

POWER

COMBINER

POWER

COMBINER

DIFFERENTIAL

SIGNAL

SOURCE

CIRCUIT

UNDER

TEST

DATAIN

DATAIN

0.47

µF

0.47

µF

50

Ω

50

Ω

75

Ω

180

Ω

1.0

µF

FILTER

NOISE

SOURCE

GND

–5.2 V

∑

∑

Figure 2. Bit Error Rate vs. Signal-to-Noise Ratio Test:

Block Diagram

0

–10

–20

1

10

1000

100

–15

–5

JITTER FREQUENCY – kHz

1.3 UI

INPUT

JITTER

0.3 UI

INPUT JITTER

TYPE A

MASK

INPUT

JITTER

CCITT TYPE B

MASK

Figure 3. Jitter Transfer – Bandwidth

–1

–5

110

–3

JITTER FREQUENCY – kHz

1.3 UI

INPUT JITTER

0.3 UI

INPUT JITTER

CCITT

TYPE A MASK

INPUT JITTER

Figure 4. Jitter Transfer – Peaking

100

1

0.1

1

1000

100

10

0.1

10

FREQUENCY – kHz

CCITT TYPE A MASK

Figure 5. Jitter Tolerance

E-1

E-2

E-15

89

21

20

19

18

17

16

15

14

13

11

10

12

3

4

5

6

8

10

12

5E-2

3E-2

2E-2

5E-3

3E-3

2E-3

5E-4

3E-4

2E-4

22 23 24

S/N – dB

80mV

ECL

20mV

Figure 6. Bit Error Rate vs. Signal-to-Noise Ratio

0

400

1.5

0.5

–200

1.0

2.0

200

0

I

A

V

V

I

OUT

V

CC

V

EE

= –5.2V

AD805

Figure 7. VCXO Control Voltage vs. Load

OBSOLETE