ADV3002 datasheet(13/28 Pages) AD

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Data Sheet

ADV3002

Rev. B | Page 13 of 28

For example, interlayer vias can be used to route the ADV3002

TMDS outputs on multiple layers of the printed circuit board

(PCB) without severely degrading the quality of the output signal.

The output has a disable feature that places the outputs in tristate

mode. Bigger wire-OR’ed arrays can be constructed using the

ADV3002 in this mode.

The ADV3002 requires output termination resistors when the high

speed outputs are enabled. Termination can be internal and/or

external. The internal terminations of the ADV3002 are enabled

by default after reset. External terminations can be provided either

by on-board resistors or by the input termination resistors of an

HDMI/DVI receiver. If both the internal terminations are enabled

and external terminations are present, set the output current level

to 20 mA by programming the TX_OCL bit of the TMDS output

control register, as shown in Table 10 (20 mA is the default

upon reset). If only external terminations are provided (if the

internal terminations are disabled), set the output current level

to 10 mA by programming the TX_OCL bit of the TMDS output

control register. The high speed outputs must be disabled if

there are no output termination resistors present in the system.

DDC BUFFERS

The DDC buffers are 5 V tolerant bidirectional lines that carry

extended display identification data (EDID) and high bandwidth

digital content protection (HDCP) encryption. The ADV3002

provides switching and buffering for the DDC buses. The DDC

buffers are bidirectional, and fully support arbitration, clock

synchronization, and other relevant features of a standard

mode I2C bus.

EDID REPLICATION

The ADV3002 EDID replication feature reduces the total system

cost by eliminating the need for an EDID EEPROM for each

HDMI port. With the ADV3002, only a single external EDID is

necessary. The ADV3002 stores the EDID information in an

on-chip SRAM. This enables the EDID information to be simulta-

neously accessible to all four HDMI ports. The ADV3002

combines the 5 V power from the four HDMI sources such that

the EDID information can be available even when the system

power is off. A block diagram of the ADV3002 DDC buffering

and EDID replication scheme is shown in Figure 27.

HDMI

PORT A

HDMI

PORT B

HDMI

PORT C

HDMI

PORT D

SRAM

EDID

CONTROL

I2C

MASTER

EXTERNAL

EDID

EEPROM

v1.3

MCU

I2C

READ/

WRITE

SLAVE

I2C

READ/

WRITE

SLAVE

I2C

READ

SLAVE

I2C

READ

SLAVE

DDC

MUX

HDMI

I2C

READ

SLAVE

EDID_[SCL/SDA]

I2C_[SCL/SDA]

Figure 27. EDID Replication Block Diagram

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