ADV3002 datasheet(24/28 Pages) AD

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ADV3002

Data Sheet

Rev. B | Page 24 of 28

CABLE LENGTHS AND EQUALIZATION

The ADV3002 offers two levels of programmable equalization

for the high speed inputs: 4 dB and 16 dB. The equalizer of the

ADV3002 supports video data rates of up to 2.25 Gbps and can

equalize more than 15 meters of 24 AWG HDMI cable at

2.25 Gbps, which corresponds to the video format, 1080p with 12-

bit Deep Color. The length of cable that can be used in a typical

HDMI/ DVI application depends on a large number of factors

including

•

Cable quality: the quality of the cable in terms of conductor

wire gauge and shielding. Thicker conductors have lower

signal degradation per unit length.

•

Data rate: the data rate being sent over the cable. The signal

degradation of HDMI cables increases with data rate.

•

Edge rates: the edge rates of the source input. Slower input

edges result in more significant data eye closure at the end

of a cable.

•

Receiver sensitivity: the sensitivity of the terminating

receiver.

As such, no particular equalizer setting is recommended for

specific cable types or lengths. In nearly all applications, the

ADV3002 equalization level can be set to high, or 18 dB, for all

input cable configurations at all data rates, without degrading the

signal integrity.

PCB LAYOUT GUIDELINES

The ADV3002 switches two distinctly different types of signals,

both of which are required for HDMI and DVI video. These

signal groups require different treatment when laying out a PCB.

The first group of signals carries the A/V data. HDMI/DVI video

signals are differential, unidirectional, and high speed (up

to 2.25 Gbps). The channels that carry the video data must be

controlled impedance, terminated at the receiver, and capable of

operating up to at least 2.25 Gbps. It is especially important to

note that the differential traces that carry the TMDS signals should

be designed with a controlled differential impedance of 100 Ω. The

ADV3002 provides single-ended 50 Ω terminations on-chip for

both its inputs and outputs, and both the input and output

terminations can be enabled or disabled through the serial

interface. Output termination is recommended but not required by

the HDMI standard but its inclusion improves the overall system

signal integrity.

The A/V data carried on these high speed channels is encoded

by a technique called TMDS, and in the case of HDMI, is also

encrypted according to the HDCP standard.

The second group of signals consists of low speed auxiliary

control signals used for communication between a source and a

sink. Depending upon the application, these signals can include

the DDC bus (this is an I2C bus used to send EDID information

and HDCP encryption keys between the source and the sink),

the CEC line, and the HPD line. These auxiliary signals are

bidirectional, low speed, and transferred over a single-ended

transmission line that does not need to have controlled impedance.

The primary concern with laying out the auxiliary lines is ensuring

that they conform to the I2C bus standard and do not have

excessive capacitive loading.

TMDS Signals

In the HDMI/DVI standard, four differential pairs carry the

TMDS signals. In DVI, three of these pairs are dedicated to

carrying RGB video and sync data. For HDMI, audio data

interleaves with the video data; the DVI standard does not incor-

porate audio information. The fourth high speed differential pair

is used for the A/V data-word clock, and runs at one-tenth the

speed of the TMDS data channels.

The ADV3002 buffers the TMDS signals, and the input traces

can be considered electrically independent of the output traces.

In most applications, the quality of the signal on the input

TMDS traces are more sensitive to the PCB layout. Regardless

of the data being carried on a specific TMDS channel, or

whether the TMDS line is at the input or the output of the

ADV3002, all four high speed signals should be routed on a

PCB in accordance with the same RF layout guidelines.

Layout for the TMDS Signals

The TMDS differential pairs can be either microstrip traces

(routed on the outer layer of a board) or stripline traces (routed

on an internal layer of the board). If microstrip traces are used,

there should be a continuous reference plane on the PCB layer

directly below the traces. If stripline traces are used, they must

be sandwiched between two continuous reference planes in the

PCB stack-up. Additionally, the p and n of each differential pair

must have a controlled differential impedance of 100 Ω. The

characteristic impedance of a differential pair is a function of

several variables including the trace width, the distance separating

the two traces, the spacing between the traces and the reference

plane, and the dielectric constant of the PCB binder material.

Interlayer vias introduce impedance discontinuities that can

cause reflections and jitter on the signal path; therefore, it is

preferable to route the TMDS lines exclusively on one layer of the

board, particularly for the input traces. Additionally, to prevent

unwanted signal coupling and interference, route the TMDS

signals away from other signals and noise sources on the PCB.

Both traces of a given differential pair must be equal in length

to minimize intrapair skew. Maintaining the physical symmetry

of a differential pair is integral to ensuring its signal integrity;

excessive intrapair skew can introduce jitter through duty cycle

distortion (DCD). Always route the p and n of a given differen-

tial pair together to establish the required 100 Ω differential

impedance. Leave enough space between the differential pairs

of a given group to prevent the n of one pair from coupling with

the p of another pair. For example, one technique is to make the

interpair distance four to 10 times wider than the intrapair spacing.

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