LPC84X datasheet(6/97 Pages) NXP

6 / 97 page

LPC84x

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Product data sheet

Rev. 1.7 — 27 February 2018

6 of 97

NXP Semiconductors

LPC84x

32-bit Arm Cortex-M0+ microcontroller

6. Block diagram

Gray-shaded blocks show peripherals that can provide hardware triggers or fixed DMA requests for DMA transfers.

Fig 3.

LPC84x block diagram

aaa-022793

CLKOUT

Vdd

CLKIN

XTALIN

XTALOUT

SWD Port

JTAG Test and

Boundary Scan

interface

RESET

Clock Generation,

Power Control,

and other

System Functions

Voltage Regulator

DEBUG

INTERFACE

IOP bus

GPIOs

GPIOs AND

GPOINT

Flash

interface

Flash

64 kB

General

Purpose

DMA

controller

MTB slave

interface

DMA

registers

CRC

Multilayer

AHB Matrix

AHB to

APB bridge

FAIM

256-bit

T0 Match/

Capture

I2C2,3

COMP

Inputs

ADC Inputs

and Triggers

DAC1 outputs

DAC0 outputs

PIOs

UART0,1,2, 3,4

CAPT

SPI0,1

I2C0,1

APB slave group

Watchdog

Osc

Windowed WDT

Note:

SCT Timer/

PWM

ARM

Cortex M0+

System control

IOCON Registers

Flash Registers (NVMC)

CTIMER32

I2Cs 2 and 3

UARTs 0-4

CapTouch

SPIs 0 and 1

I2Cs 0 and 1

Periph Input Mux Selects

Comparator

PMU Registers

12-bit ADC

10-bit DAC1

10-bit DAC0

FAIM Registers

Switch Matrix

Wakeup Timer

Multi-Rate Timer

Boot ROM

16 kB

SRAM/MTB

8 kB

SRAM

8 kB

Yellow shaded blocks support general purpose DMA

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