ICS8305 Data Sheet

LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER

ICS8305AG REVISION C MAY 30, 2014

2

©2014 Integrated Device Technology, Inc.

Table 1. Pin Descriptions

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Number

Name

Type

Description

1, 9, 13

GND

Power

Power supply ground

2

OE

Input

Pullup

Output enable. When LOW, outputs are in HIGH impedance state.

When HIGH, outputs are active. LVCMOS/LVTTL interface levels.

Power

Power supply pin.

4

CLK_EN

Input

Pullup

Synchronizing clock enable. When LOW, the output clocks are disabled.

When HIGH, output clocks are enabled. LVCMOS/LVTTL interface levels.

5

CLK

Input

Pulldown

Non-inverting differential clock input.

6

nCLK

Input

Pullup/

Pulldown

Inverting differential clock input. VDD/2 default when left floating.

7

CLK_SEL

Input

Pullup

Clock select input. When HIGH, selects CLK, nCLK inputs. When LOW,

selects LVCMOS_CLK input. LVCMOS/LVTTL interface levels.

8

LVCMOS_CLK

Input

Pulldown

Single-ended clock input. LVCMOS/LVTTL interface levels.

10, 12, 14, 16

Q3, Q2, Q1, Q0

Output

Single-ended clock outputs. 7

LVCMOS/LVTTL interface levels.

11, 15

Power

Output supply pins.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Input Capacitance

4

pF

Input Pullup Resistor

51

k



Input Pulldown Resistor

51

k



Power Dissipation Capacitance

(per output)

11

pF

Output Impedance

7

