ICS8305 Data Sheet

LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER

ICS8305AG REVISION C MAY 30, 2014

6

©2014 Integrated Device Technology, Inc.

AC Electrical Characteristics

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium

has been reached under these conditions.

All parameters measured at ƒ

 350MHz unless noted otherwise.

NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using

NOTE 4: These parameters are guaranteed by characterization. Not tested in production.

NOTE 5: Driving only one input clock.

NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.

For NOTES, see Table 5A above.

Parameter

Symbol

Test Conditions

Minimum

Typical

Maximum

Units

Output Frequency

350

MHz

Propagation

Delay,

Low to High

LVCMOS_CLK;

NOTE 1A

CLK/nCLK;

NOTE 1B

1.75

2.75

ns

tsk(o)

Output Skew; NOTE 2, 6

Measured on the Rising Edge

35

ps

tsk(pp)

Part-to-Part Skew; NOTE 3, 6

700

ps

tjit

Buffer Additive Phase Jitter, RMS;

refer to Additive Phase Jitter

Section, NOTE 5

0.04

ps

Output Rise/Fall Time;

NOTE 4

20% to 80%

100

700

ps

odc

Output Duty Cycle

Ref = CLK/nCLK

45

55

%

Ref = LVCMOS_CLK, ƒ

 300MHz

45

55

%

Output Enable Time; NOTE 4

5ns

Output Disable Time; NOTE 4

5ns

Parameter

Symbol

Test Conditions

Minimum

Typical

Maximum

Units

Output Frequency

350

MHz

Propagation

Delay,

Low to High

LVCMOS_CLK;

NOTE 1A

CLK/nCLK;

NOTE 1B

1.8

2.9

ns

tsk(o)

Output Skew; NOTE 2, 6

Measured on the Rising Edge

35

ps

tsk(pp)

Part-to-Part Skew; NOTE 3, 6

800

ps

tjit

Buffer Additive Phase Jitter, RMS;

refer to Additive Phase Jitter

Section, NOTE 5

0.04

ps

Output Rise/Fall Time; NOTE 4

20% to 80%

100

700

ps

odc

Output Duty Cycle

Ref = CLK/nCLK

44

56

%

Ref = LVCMOS_CLK, ƒ

 300MHz

44

56

%

Output Enable Time; NOTE 4

5ns

Output Disable Time; NOTE 4

5ns