ICS8305 Data Sheet

LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER

ICS8305AG REVISION C MAY 30, 2014

14

©2014 Integrated Device Technology, Inc.

Reliability Information

NOTE: Most modern PCB design use multi-layered boards. The data in the second row pertains to most designs.

Transistor Count

The transistor count for ICS8305: 459

Package Outline and Package Dimensions

Package Outline - G Suffix for 16 Lead TSSOP

Table 7. Package Dimensions for 16 Lead TSSOP

Reference Document: JEDEC Publication 95, MO-153



Linear Feet per Minute

0200

500

Single-Layer PCB, JEDEC Standard Test Boards

137.1°C/W

118.2°C/W

106.8°C/W

Multi-Layer PCB, JEDEC Standard Test Boards

89.0°C/W

81.8°C/W

78.1°C/W

All Dimensions in Millimeters

Symbol

Minimum

Maximum

N

16

A

1.20

A1

0.5

0.15

A2

0.80

1.05

b

0.19

0.30

c

0.09

0.20

D

4.90

5.10

E

6.40 Basic

E1

4.30

4.50

e

0.65 Basic

L

0.45

0.75



0°

8°

aaa

0.10