AD9508 datasheet(20/40 Pages) AD

20 / 40 page

AD9508

Data Sheet

Rev. G | Page 20 of 40

TEST CIRCUITS

INPUT/OUTPUT TERMINATION RECOMMENDATIONS

Figure 34. Typical AC-Coupled or DC-Coupled LVDS or HSTL Configurations

Figure 35. Typical AC-Coupled or DC-Coupled CML Configurations

Figure 36. Typical AC-Coupled or DC-Coupled LVPECL Configurations

Figure 37. Typical 2.5 V or 3.3 V CMOS Configurations for Short Trace Lengths

Figure 38. 1.8 V CMOS Logic Configuration for Input Clock Using Differential

Mode

Figure 39. AC-Coupled LVDS or HSTL Output Driver (100 Ω Resistor Can Go

on Either Side of Decoupling Capacitors Placed As Close As Possible To The

Destination Receiver)

Figure 40. DC-Coupled LVDS or HSTL Output Driver

Figure 41. Interfacing the HSTL Driver to a 3.3 V LVPECL Input (This Method

Incorporates Impedance Matching and DC Biasing for Bipolar LVPECL

Receivers. If the Receiver Is Self-Biased, the Termination Scheme Shown in

Figure 39 Is Recommended.)

100

Ω

CLK

100

Ω

CLK

AD9508

CLK

VCC

AD9508

CLK

Ω 50Ω

VCC – 2V

CLK

Ω 50Ω

AD9508

VCC – 2V

CLK

AD9508

0.1µF

LOGIC 1

0.1µF

1.8V CMOS DRIVER

IN_SEL

CLK

AD9508

DOWNSTREAM

DEVICE

WITH HIGH

IMPEDANCE

INPUT AND

INTERNAL

DC-BIAS

0.1µF

100

Ω

AD9508

HSTL OR

LVDS

AD9508

HSTL OR

LVDS

Z0 = 50Ω

SINGLE-ENDED

(NOT COUPLED)

LVDS OR 1.8V HSTL

HIGH-IMPEDANCE

DIFFERENTIAL

RECEIVER

100

Ω

3.3V

LVPECL

0.1µF

AD9508

1.8V

HSTL

Z0 = 50Ω

SINGLE-ENDED

(NOT COUPLED)

Ω

VS = 3.3V

Ω

127

Ω

127

Ω

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