AD9508 datasheet(23/40 Pages) AD

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Data Sheet

AD9508

Rev. G | Page 23 of 40

CLOCK INPUT

The IN_SEL pin controls the desired input clock configuration.

When the IN_SEL pin is set for single-ended operation, the device

expects 1.8 V (if ac-coupled), 2.5 V, or 3.3 V CMOS-compatible

logic levels on the CLK input pin. Bypass the unused CLK pin

to ground with a 0.1 µF capacitor.

Note that if 2.5 V CMOS logic is used for single-ended input

clock mode, the 2.5 V power supply option is recommended

instead of 3.3 V operation to avoid possible duty cycle distortion.

Duty cycle distortion can occur when the switching threshold

level (VDD/2 or 1.65 V for 3.3 V operation) is increased and

slow rise and falls times exist at the clock input.

1.8 V CMOS logic levels are not recommended in a single-ended

CMOS configuration due to VIH being too close to the input

threshold voltage. However, the differential input clock mode

can be used for a 1.8 V CMOS input, and Figure 38 shows the

recommended configuration for a 1.8 V CMOS input clock.

When the IN_SEL pin is set for differential input clock mode,

the inputs of the AD9508 are internally self biased. The internal

inputs have a resistor divider, which sets the common-mode

level. The complementary input is biased about 30 mV lower

than the true input to avoid oscillations in the event that the

input signal ceases. See Figure 43 for the equivalent differential

input circuit.

Figure 43. AD9508 Differential Input Stage

The inputs can be ac-coupled or dc-coupled in differential

mode. See Table 14 for input logic compatibility. The user can

supply a single-ended input with the input in differential mode

by ac or dc coupling to one side of the differential input and

bypassing the other input to ground by a capacitor.

Note that jitter performance degrades with low input slew rate,

as shown in Figure 25. See Figure 34 through Figure 37 for

different input clock termination schemes.

Table 14. CLK and CLK Differential Input Logic Compatibility

Input Logic Type

Input Common Mode (V)

Input Voltage Swing (per leg) (V)

AC-Coupled

DC-Coupled

3.3 V CML

2.9

0.8

Yes

Not allowed

2.5 V CML

2.1

0.8

Yes

Not allowed

1.8 V CML

1.4

0.8

Yes

3.3 V CMOS1

1.65

3.3

Not allowed

Yes

2.5 V CMOS1, 2

1.25

2.5

Not allowed

Yes

1.8 V CMOS3

0.9

1.8

Yes

Not recommended

1.5 V HSTL

0.75

Yes

LVDS

1.25

0.4

Yes

3.3 V LVPECL

2.0

0.8

Yes

Not allowed

2.5 V LVPECL

1.2

0.8

Yes

1 IN_SEL is set for single-ended CMOS mode.

2 VDD = 2.5 V operation recommended vs. VDD = 3.3 V operation.

3 Refer to Figure 38 for configuration.

12.5kΩ

13kΩ

16.5kΩ

16kΩ

VDD

CLK

GND

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